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DELD Lab Assignment 4

The document discusses the design and implementation of MOD 10, MOD 100 and MOD N counters using the 7490 integrated circuit. It describes how a MOD 10 counter can be made using one 7490 IC by cascading its internal MOD-2 and MOD-5 counters. A MOD 100 counter can be designed by cascading two 7490 ICs, with the tens place IC clocked by the carry output of the units place IC. The 7490 IC and cascading technique can be used to create MOD N counters of any desired modulus N.

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Sahil Jaiswal
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80 views

DELD Lab Assignment 4

The document discusses the design and implementation of MOD 10, MOD 100 and MOD N counters using the 7490 integrated circuit. It describes how a MOD 10 counter can be made using one 7490 IC by cascading its internal MOD-2 and MOD-5 counters. A MOD 100 counter can be designed by cascading two 7490 ICs, with the tens place IC clocked by the carry output of the units place IC. The 7490 IC and cascading technique can be used to create MOD N counters of any desired modulus N.

Uploaded by

Sahil Jaiswal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 15

Assignment Number: 04

PROBLEM STATEMENT: Design and implement MOD


10, MOD 100 and MOD N counter using IC 7490.
 

11/14/2022 CSE 213 - Digital Electronics and Logic Design 1


OBJECTIVES

• To understand working of Modulo N counter


using 7490(N>10).

11/14/2022 CSE 213 - Digital Electronics and Logic Design 2


Modulus ‘n’ counter
▶ The number of flip-flops determines the count limit or number of
states in a counter.
▶ If N flip-flops are connected:
No. of states = 2N where N = number of flip-flops
▶ The number of states used is called the MODULUS

▶ Modulus Counters, or simply MOD counters, are defined based on


the number of states that the counter will sequence through before
returning back to its original value

▶ For example, a Modulus-12 counter (Mod-12) would count from 0


(00002) to 11 (10112) and would require four flip-flops (24 = 16
states; 12 are used)
11/14/202 CSE 213 - Digital Electronics and Logic Design 3
2
Modulus ‘n’ counter
▶ Power-of-2 counters use all states
▶ Example: 4-bit Binary / Hex / Mod-16 Counter
▶ 0000, 0001, 0010, … 1110, 1111, 0000, 0001, …
all states used

▶ Non-power-of-2 counters have extra, unused


states
▶ Example: 4-bit BCD / Decade / Mod-10 Counter
▶ 0000, 0001, 0010, … 1000, 1001, 0000, 0001, …
six unused states

11/14/2022 CSE 213 - Digital Electronics and Logic Design 4


Feature of IC 7490 MOD

▶ IC 7490 is a TTL MSI (medium scale integration) decade counter.


▶ It is an asynchronous counter
▶ It contains 4 master slave flip flops internally connected to provide
MOD-2 i.e. divide by 2 and MOD-5 i.e. divide by 5 counters.
▶ MOD-2 and Mod-5 counters can be used independently or in
cascading.
▶ It is a 4-bit ripple type decade counter.
▶ It is also called as Divide by 10 counter as frequency at the MSB
(QD) is 1/10*fclk

11/14/2022 CSE 213 - Digital Electronics and Logic Design 5


Pin Out of 7490

11/14/2022 CSE 213 - Digital Electronics and Logic Design 6


Internal Diagram of IC 7490

11/14/2022 CSE 213 - Digital Electronics and Logic Design 7


Function Table of MOD-2 and MOD - 5 counter

▶ Function Table
 
Output
Input B Count
Input A Output Count clock QD QC QB
clock QA
 
    0 0 0 0
0 0
0 0 1 1
 
   
0 1 0 2
1 1
0 1 1 3

1 0 0 4

11/14/2022 CSE 213 - Digital Electronics and Logic Design 8


BCD Decade(MOD-10) Counter using IC 7490

11/14/2022 CSE 213 - Digital Electronics and Logic Design 9


BCD Decade(MOD-10) Counter using IC 7490
State Diagram

11/14/2022 CSE 213 - Digital Electronics and Logic Design 10


Design of BCD Decade Counter using IC 7490
I/p Output  
clock
QD QC QB QA Count
The QA o/p the first flip flop is
  connected to the input B which is
 
clock i/p of internal MOD-5
0 0 0 0 0 ripple counter.
0 0 0 1 1
0 0 1 0 2
Due to cascading of Mod-2 and
0 0 1 1 3
0 1 0 0 4
Mod-5 counters, the overall
0 1 0 1 5 configuration the decade counters
0 1 1 0 6 count from 0000 to 1001.
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
After 1001 mod-5 resets to 0000
and next count after 1001 is
11/14/2022 0000. 11
CSE 213 - Digital Electronics and Logic Design
Timing diagram of mod10 Counter

11/14/2022 CSE 213 - Digital Electronics and Logic Design 12


Cascading of IC 7490
• To get the BCD counter which can count more than 10 pulses,
cascading of IC 7490 is done.
• Multiple ICs can be cascaded together to get required count.
• Each cascaded IC is a decade counter ( QA connected to CLK B)
• MSB output (QD) of first IC is connected as CLK A of second IC
• Two cascaded ICs can count up to 100 states (0 to 99)
• Three cascaded ICs can count up to 1000states (0 to 999) and so
on

11/14/2022 13
CSE 213 - Digital Electronics and Logic Design
Design of Mod-100 Counter using IC 7490

▶ The MOD-100 counter will count 100 states from 0 to 99.

▶ One IC 7490 can count from 0 to 9.

▶ For Mod-100 counter, two ICs of 7490 will be required. One for
Unit’s place and one for Ten's place

▶ Cascading two BCD counters in such a way that after the Unit’s
place IC counts from 0 to 9, ten’s place IC will increment once will
suffice the requirement.

▶ No separate reset logic is required

11/14/2022 CSE 213 - Digital Electronics and Logic Design 14


Design of Mod-100 Counter using IC 7490

MSB

Input B
Input B
R1 = R0 1
Clock R2 = R0 2
input S1 = R9 1
S2 = R9 2

Unit’s Place Ten’s Place

As input clock is given to Unit Place IC, it will count from 0 to 9.


When QD of IC 1 will go from 1 to 0 in next clock pulse, IC 2 will get clock at its input A and second IC will
count 1.

Second IC will get clock only when first IC will count from 0 to 9 (i.e. after every 10 clock pulses).
Thus the counter will reach to 99 before resetting to 00
11/14/2022 CSE 213 - Digital Electronics and Logic Design 15

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