Digital Logic & Processors

Memory Unit – Flip-flops

 Sequential Circuits

Inputs Outputs

Combinational
Circuit

Flip-flops
Clock

2
11/12/22 Source: Confidential 3
 Memory Unit
• The flip-flop is the basic unit of digital memory.

• A flip-flop can store one bit of data.

• Sets of flip-flops are called registers and can hold bytes of data.

• Sets of registers are called memories, and can hold many

thousands of bits, or more.

11/12/22
 LATCH
• A latch is an electronic logic circuit that has two inputs
and one output.
• One of the inputs is called the SET input; the other is
called the RESET input.
• Output depends not only on the current inputs, but also
on previous outputs.
• It has two stable states (HIGH or LOW).
• They act as memory devices and can store one bit of
data.
11/12/22 Source: Confidential 5
 Types of LATCHES
NOR LATCH NAND LATCH

11/12/22 Source: Confidential 6

 Types of LATCHES
NOR LATCH NAND LATCH

Truth Table Truth Table

When any one input is HIGH output is LOW. When any one input is LOW output is HIGH.
S R Q State S R Q State
0 0 Q NC 0 0 1 1 NA
0 1 0 1 Reset 0 1 1 0 Set
1 0 1 0 Set 1 0 0 1 Reset
1 1 0 0 NA 1 1 Q NC

11/12/22 Source: Confidential 7

Types of Triggering
•Level Triggering
•Edge Triggering

8
 Working of S R LATCH with NOR Gate (Q to S & Qbar to R)
Case 1: Case 3: Case 4:
1 0 1
0 1 0
Reset Set Not Allowed

0 1 1 0 1 0

Case 2: Case 2: Truth Table

0 0 0 S R Q State
1
0 0 Q NC
No Change No Change 0 1 0 1 Reset

1 0 1 0 1 0 Set
0 0 1 1 0 0 NA

11/12/22 Source: Confidential 9

 Case 1: R = 1 and S = 0
• In this case, the ‘R’ input is 1, which means the output of the NOR Gate A will
become 0 i.e., Q is 0 (LOW). As a result, both the inputs of NOR Gate B become 0
and hence the output of the NOR Gate B is 1 (HIGH). As ‘1’ at input R makes the
output to switch to one of its stable states and resets it to ‘0’, the R input is known as
RESET input.

Case 2: R = 0 and S = 0
• In this case, the inputs of both the NOR gates are Logic ‘0’. As neither of them are
dominating inputs, they have no effect on the output. So, the output retains their
previous states i.e., there is no change in the output. This condition is called as Hold
Condition or No Change Condition.

11/12/22 Source: Confidential 10

 Case 3: R = 0 and S = 1
• In this case, the ‘S’ input is 1, which means the output of the NOR Gate B will
become 0. As a result, both the inputs of NOR Gate A become 0 and hence the output
of the NOR Gate A and thus the value of Q is 1 (HIGH). As ‘1’ at input S makes the
output to switch to one of its stable states and sets it to ‘1’, the S input is known as
SET input.

Case 2: R = 0 and S = 0
• In this case, the inputs of both the NOR gates are Logic ‘0’. As neither of them are
dominating inputs, they have no effect on the output. So, the output retains their
previous states i.e., there is no change in the output. This condition is called as Hold
Condition or No Change Condition.

11/12/22 Source: Confidential 11

 Case 4: R = 1 and S = 1
• This input condition is forbidden as it forces outputs of both NOR Gates to become 0,
which is a violation of complementary outputs. Even if this input condition is applied, if
the next inputs become R = 0 and S = 0 (hold condition), then it causes a ‘race condition’
between the NOR Gates, which causes an unstable or unpredictable state at the output.
• Hence, the input condition R = 1 and S = 1 is simply not used.

11/12/22 Source: Confidential 12

 S R Latch with NOR gate
S R Qn Qn+1 State
0 0 0 0 NC
0 0 1 1 NC
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
1 1 0 NA NA
1 1 1 NA NA

11/12/22 Source: Confidential 13

 Working of S R LATCH with NAND Gate (Qbar to S & Q to R)
Case 1: S = 0 & R = 1 Case 3: S = 1 & R = 0 Case 5: S = 0 & R = 0

1 1 1
Set

0 0 1

Case 2: S = 1 & R = 1 Case 4: S = 1 & R = 1

1 1
S R Q State
No Change 0 0 1 1 NA
0 1 1 0 Set
0 0 1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 14

 S R Latch with NAND gate
S R Qn Qn+1 State
0 0 0 NA NA
0 0 1 NA NA
0 1 0 1 Set
0 1 1 1 Set
1 0 0 0 Reset
1 0 1 0 Reset
1 1 0 0 NC
1 1 1 1 NC

11/12/22 Source: Confidential 15

 Latches Vs Flipflops

11/12/22 Source: Confidential 16

 S R Flip Flop
Circuit Diagram
Block Diagram

CLK

11/12/22 Source: Confidential 17

 S R Flip Flop
S*

CLK

R*

11/12/22 Source: Confidential 18

 S R Flip Flop
Truth Table
CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory
0 1 0 1 Reset
1 0 1 0 Set
1 1 Not
NA NA
Allowed
S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 19

 Working of S R Flip Flop using NAND Gates
Case 1: S = 0 & R = 0 CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory

S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 20

 Working of S R Flip Flop using NAND Gates
Case 2: S = 0 & R = 1 CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory
0 1 0 1 Reset

S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 21

 Working of S R Flip Flop using NAND Gates
Case 3: S = 1 & R = 0 CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory
0 1 0 1 Reset
1 0 0 1 Set

S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 22

 Working of S R Flip Flop using NAND Gates
Case 4: S = 1 & R = 1 CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory
0 1 0 1 Reset
1 0 1 0 Set
1 1 Not
1 1
Allowed

S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 23

 S R Flip Flop
Truth Table
CLK S R Q Q State
0 X X Q Q
0 0 NC NC Memory
0 1 0 1 Reset
1 0 1 0 Set
1 1 Not
NA NA
Allowed
S* R* Q State
0 0 1 1 NA
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q NC

11/12/22 Source: Confidential 24

 S R Flip-Flop Characteristic Table
PS NC Characteristic Equation
CLK S R
Qn Qn+1 Remarks
0 0 0 0 No
0 0 1 1 Change
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X Not
1 1 1 X Allowed

11/12/22 Source: Confidential 25

 S R Flip-Flop Excitation Table
PS NC PS NC Inputs
CLK S R
Qn Qn+1 Remarks Qn Qn+1 S R
0 0 0 0 No 0 0 0 X
0 0 1 1 Change 0 1 1 0
0 1 0 0 1 0 0 1
Reset
0 1 1 0 1 1 X 0
1 0 0 1
Set
1 0 1 1
1 1 0 X Not
1 1 1 X Allowed

11/12/22 Source: Confidential 26

 D Flip Flop
• Delay Flip Flop

• An SR FF is converted to D FF by connecting a NOT gate

between S & R inputs.

• With the addition of a NOT gate the NOT ALLOWED (S=1,

R=1) state can be avoided.

• The FF has only one input.

11/12/22 Source: Confidential 27
 D Flip Flop
Circuit Diagram Block Diagram

11/12/22 Source: Confidential 28

 D Flip Flop Truth Table D Flip Flop Truth Table

CLK D CLK D Qn Qn+1 Sate

1 0 0 1 1 0 X 0 Reset
1 1 1 0 1 1 X 1 Set

D Flip Flop Characteristic Table

D Flip Flop Characteristic Equation
CLK D Qn Qn+1 State
1 0 0 0 Reset
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 1 Set
0 X 0 0 NC
0 X 1 1 NC

11/12/22 Source: Confidential 29

 D Flip Flop Characteristic Table D Flip Flop Excitation Table

CLK D Qn Qn+1 State PS NS Input

1 0 0 0 Reset Qn Qn+1 D
1 0 1 0 Reset 0 0 0
1 1 0 1 Set 0 1 1
1 1 1 1 Set 1 0 0
0 X 0 0 NC 1 1 1
0 X 1 1 NC

11/12/22 Source: Confidential 30

 J K Flip Flop
• The working of JK FF is same as that of SR FF (S=J &
R=K).
• To overcome the disadvantage of SR and D FF.
• .

• D FF has only two possible combinations.

• .

• SR FF S=1 and R=1 is Not Allowed condition.

• It has no invalid state.
• It has TOGGLE state.
11/12/22 Source: Confidential 31
 J K Flip Flop

11/12/22 Source: Confidential 32

 J K Flip Flop

CLK

11/12/22 Source: Confidential 33

 J K Flip Flop
CLK J K Qn Qn+1 State
1 0 0 X Qn NC
1 0 1 X 0 Reset
1 1 0 X 1 Set
1 1 1 X 1,0 Toggle
CLK

CLK J K State
1 0 0 NC
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 X 1,0 Toggle

11/12/22 Source: Confidential 34

CLK

11/12/22 Source: Confidential 35

 J K FF Characteristic Table
PS NS
J K FF Characteristic Equation
CLK J K Qn Qn+1 State
1 0 0 0 0 NC
1 0 0 1 1 NC
1 0 1 0 0 Reset
1 0 1 1 0 Reset
1 1 0 0 1 Set
1 1 0 1 1 Set
1 1 1 0 1 Toggle
1 1 1 1 0 Toggle

11/12/22 Source: Confidential 36

 J K FF Excitation Table
PS NS PS NC Inputs
CLK J K Qn Qn+1 State Qn Qn+1 J K
1 0 0 0 0 NC 0 0 0 X
1 0 0 1 1 NC 0 1 1 X
1 0 1 0 0 Reset 1 0 X 1
0 Reset 1 1 X 0
1 0 1 1
1 1 0 0 1 Set
1 1 0 1 1 Set
1 1 1 0 1 Toggle
1 1 1 1 0 Toggle

11/12/22 Source: Confidential 37

 T Flip Flop
• Known as Toggle Flip Flop.
• Constructed by connecting J & K inputs.

11/12/22 Source: Confidential 38

 T Flip Flop

11/12/22 Source: Confidential 39

 T Flip Flop

11/12/22 Source: Confidential 40

 J

11/12/22 Source: Confidential 41

 T Flip Flop Truth Table T Flip Flop Truth Table

CLK T CLK T Qn Qn+1 Sate

1 0 0 1 1 0 0 0 No
1 0 1 0 1 0 1 1 Change
1 1 0 1 1 1 0 1
Toggle
1 1 1 0 1 1 1 0

T Flip Flop Characteristic Table

T Flip Flop Characteristic Equation
CLK T Qn Qn+1 State
1 0 0 0 NC
1 0 1 1 NC
1 1 0 1 Toggle
1 1 1 0 Toggle
0 X 0 0 NC
0 X 1 1 NC
11/12/22 Source: Confidential 42
T Flip Flop Characteristic Table
T Flip Flop Characteristic Equation
CLK T Qn Qn+1 State
1 0 0 0 NC PS NS Input
1 0 1 1 NC Qn Qn+1 T
1 1 0 1 Toggle 0 0 0
1 1 1 0 Toggle 0 1 1
0 X 0 0 NC 1 0 1
0 X 1 1 NC 1 1 0

11/12/22 Source: Confidential 43

 SR FF Truth, Characteristic & Excitation Tables, Characteristic
Equation
Truth Table Characteristic Table
CLK S R Q Q PS NC
0 X X CLK S R
Q Q Qn Qn+1 Remarks
0 0 NC NC 0
0 0 0 No
0 1 0 1 Change
0 0 1 1
1 0 1 0
0 1 0 0
1 1 NA NA Reset
0 1 1 0
Excitation Table
1 0 0 1
PS NC Inputs Set
1 0 1 1
Qn Qn+1 S R
1 1 0 X Not
0 0 0 X
1 1 1 X Allowed
0 1 1 0
1 0 0 1 Characteristic Equation
111/12/22 1 X 0 Source: Confidential 44
 D FF Truth, Characteristic & Excitation Tables, Characteristic Equation
Truth Table Characteristic Table
CLK D Qn Qn+1 State
CLK D 1 0 0 0 Reset
1 0 0 1 1 0 1 0 Reset
1 1 1 0 1 1 0 1 Set
1 1 1 1 Set
0 X 0 0 NC
0 X 1 1 NC
Excitation Table
PS NS Input
Qn Qn+1 D
0 0 0 Characteristic Equation
0 1 1
1 0 0
1 1 1

11/12/22 Source: Confidential 45

 JK FF Truth, Characteristic & Excitation Tables, Characteristic Equation
Truth Table Characteristic Table
CLK J K Qn Qn+1 PS NS
1 0 0 X Qn CLK J K Qn Qn+1 State
1 0 1 X 0
1 0 0 0 0 NC
1 1 0 X 1
1 1 1 X 1,0 1 0 0 1 1 NC
1 0 1 0 0 Reset
Excitation Table 1 0 1 1 0 Reset
PS NC Inputs 1 Set
1 1 0 0
Qn Qn+1 J K
1 1 0 1 1 Set
0 0 0 X
1 1 1 0 1 Toggle
0 1 1 X
1 1 1 1 0 Toggle
1 0 X 1
Characteristic Equation
1 1 X 0
11/12/22 Source: Confidential 46
 T FF Truth, Characteristic & Excitation Tables, Characteristic Equation
Truth Table Characteristic Table
CLK T Qn Qn+1 State
CLK T 1 0 0 0 NC
1 0 0 1 1 0 1 1 NC
1 0 1 0 1 1 0 1 Toggle
1 1 0 1 1 1 1 0 Toggle
1 1 1 0 0 X 0 0 NC
0 X 1 1 NC
Excitation Table
PS NS Input
Qn Qn+1 T
0 0 0 Characteristic Equation
0 1 1
1 0 1
1 1 0

11/12/22 Source: Confidential 47

 Flip-Flops with Direct Inputs
• Asynchronous Preset and Clear

PR CLR D CLK Q(t+1)

1 0 x x 0
0 1 x x 1
1 1 0 ↑ 0
1 1 1 ↑ 1

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