KCS-402

UNIT-III
MICROPROCESSOR
By: Mr. Madan Singh
UNIT III: 16-bit Microprocessors (8086) KEC-
Contents 502

• Architecture
• Pin Description
• Physical address, segmentation, memory organization
• Addressing modes
• Peripheral Devices:
• 8237 DMA Controller
• 8255 programmable peripheral interface
• 8253/8254programmable timer/counter
• 8259 programmable interrupt controller
• 8251 USART and RS232C.
 8086 Features
• 16-bit data bus
• 20-bit address bus (220 = 1,048,576 = 1M)
•The address refers to a byte in memory.
•In the 8086, bytes at even addresses come in on the low half of the data bus (bits 0-7)
and bytes at odd addresses come in on the upper half of the data bus (bits 8-15).
•The 8086 can read a 16-bit word at an even address in one operation and at an odd
address in two operations.
•The least significant byte of a word on an 8086 family of microprocessor is at the
lower address.
8086 ARCHITECTURE
BLOCK DIAGRAM

• BIU:
BUS INTERFACE
UNIT
• EU:
EXECUTION UNIT
 8086 Architecture
• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution
Unit (EU).
• The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
• The EU decodes and executes the instructions using the 16-bit ALU.
• The BIU contains the following registers:
IP - the Instruction Pointer
CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
8086 Architecture

• The BIU fetches instructions using the CS and IP, written CS:IP, to contruct
the 20-bit address.
• Data is fetched using a segment register (usually the DS) and an effective
address (EA) computed by the EU depending on the addressing mode.
 8086 ARCHITECTURE BLOCKS

•The EU contains the following 16-bit registers:

•AX - the Accumulator
•BX - the Base Register
•CX - the Count Register
•DX - the Data Register
•SP- Stack Pointer
•BP- Base pointer
•SI- Source Index Register
•DI- Destination Index Register
•These are referred to as general-purpose registers, although, as seen by their
names, they often have a special-purpose use for some instructions.
8086 ARCHITECTURE BLOCKS

•The AX, BX, CX, and DX registers can be considered as two 8-bit registers, a
High byte and a Low byte.
•This allows byte operations and compatibility with the previous generation of 8-bit
processors, the 8080 and 8085. 8085 source code could be translated in 8086 code
and assembled.
•The 8-bit registers are:
• AX --> AH,AL
• BX --> BH,BL
• CX --> CH,CL
• DX --> DH,DL
 8086
Programmer’s
Model
 Flag Register
Flag register
contains
information
reflecting the
current status of a
microprocessor.
It also contains
information which
controls the
operation of the
microprocessor.
8086 MICROPROCESSOR:
PIN DIAGRAM

• MINIMUM MODE
• MAXIMUM MODE
 MIN and MAX Modes
(Why MIN and MAX modes?)
• Min mode signals can be directly decoded by memory and I/O circuits,
resulting in a system with minimal hardware requirements.
• Max mode systems are more complicated but has the new signals that allow
for bus grants (e.g. DMA), and the use of an 8087 coprocessor.
THE PINS OF MINIMUM MODE
• ALE: address latch enable (AD0 – AD7)
• DEN: data enable (connect/disc. buffer): It stands for Data Enable and is available at pin
26. It is used to enable Transreceiver 8286. The transreceiver is a device used to separate
data from the address/data bus.
• WR: write (writing indication)
• HOLD: Hold
• HDLA: Hold acknowledge
• INTA: Interrupt acknowledge
• IO/M: Input_output/ Memory
• DT/R: It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.
THE PINS OF MAX
MODE

• S0, S1, S2: These are

the status signals that
provide the status of
operation, which is used
by the Bus Controller
8288 to generate
memory & I/O control
signals.
• These are available at
pin 26, 27, and 28. 
 THE PINS OF MAX MODE
• RQ/GT0, RQ/GT1: These are the Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When the signal is received by CPU,
then it sends acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
• LOCK: When this signal is active, it indicates to the other processors not to ask the
CPU to leave the system bus. It is activated using the LOCK prefix on any instruction
and is available at pin 29.
• QS1, QS0: These are queue status
signals and are available at pin 24
and 25. These signals provide the
status of instruction queue.
 The following are pins are available in both
minimum and maximum modes…
• Power supply and frequency signals
• It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.
• Clock signal
• Clock signal is provided through Pin-19. It provides timing to the processor for operations.
Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.
• Address/data bus
• AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit
address and after that it carries 16-bit data.
• Address/status bus
• A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries
4-bit address and later it carries status signals.
 The following are pins are available in both
minimum and maximum modes…
• Read
• It is available at pin 32 and is used to read signal for Read operation.
• Ready
• It is available at pin 22. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.
• RESET
• It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.
 The following are pins are available in both
minimum and maximum modes…
• INTR: It is available at pin 18. It is an interrupt request signal, which is sampled
during the last clock cycle of each instruction to determine if the processor
considered this as an interrupt or not.
• NMI: It stands for non-maskable interrupt and is available at pin 17. It is an edge
triggered input, which causes an interrupt request to the microprocessor.
• TEST: This signal is like wait state and is available at pin 23. When this signal is
high, then the processor has to wait for IDLE state, else the execution continues.
• MN/MX: It stands for Minimum/Maximum and is available at pin 33. It indicates
what mode the processor is to operate in; when it is high, it works in the minimum
mode and vice-aversa.
MEMORY SEGMENTATION AND ADDRESS
CALCULATION
The Bus Interface Unit (BIU) contains four 16-bit special purpose registers
(mentioned below) called as Segment Registers.
• Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
• Data segment register (DS): points to the data segment of the memory where the
data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory.
The stack segment is that segment of memory which is used to store stack data.
MEMORY SEGMENTATION
AND ADDRESS
CALCULATION

Note that the 8086 does not

work the whole 1MB
memory at any given time.
However, it works only with
four 64KB segments within
the whole 1MB memory.
One way of positioning four
64 kilobyte segments within
the 1M byte memory space
of an 8086 is shown:
 PHYSICAL ADDRESS CALCULATION

• The number of address lines in 8086 is 20, 8086 BIU will send 20-bit
address to access one of the 1MB memory locations.
• The four segment registers actually contain the upper 16 bits of the starting
addresses of the four memory segments of 64 KB each with which the
8086 is working at that instant of time.
• A segment is a logical unit of memory that may be up to 64 kilobytes long.
• Each segment is made up of contiguous memory locations.
• It is an independent, separately addressable unit.
 PHYSICAL ADDRESS CALCULATION
• The 20-bit address of a byte is called its Physical Address.
•  Logical address is in the form of:
Base Address : Offset
•  Offset is the displacement of the memory location from the starting location
of the segment.
• The value of Data Segment Register (DS) is 2222 H.
•  To convert this 16-bit address into 20-bit, the BIU appends 0H to the LSBs
of the address.
•  After appending, the starting address of the Data Segment becomes 22220H.
PHYSICAL ADDRESS CALCULATION
• If the data at any location has a logical address specified as:
2222 H : 0016 H
•  Then, the number 0016 H is the offset.
•  2222 H is the value of DS.
• To calculate the effective address of the memory, BIU uses the following
formula:
Effective Address = Starting Address of Segment + Offset
•  To find the starting address of the segment, BIU appends the contents of
Segment Register with 0H.
•  Then, it adds offset to it.
PHYSICAL ADDRESS CALCULATION
 Advantages of the Segmentation
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different
segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation
allows the use of 16-bit registers to give an addressing capability of 1
Megabytes. Without segmentation, it would require 20-bit registers.
• It is possible to enhance the memory size of code data or stack segments
beyond 64 KB by allotting more than one segment for each area.
 ADDRESSING MODES
• The different ways in which a source operand is denoted in an instruction is known
as addressing modes. There are 8 different addressing modes in 8086 programming −
• IMMEDIATE
• REGISTER
• DIRECT
• REGISTER INDIRECT
• BASE
• INDEX
• BASE-INDEX
• BASE INDEXED WITH DISPLACEMENT
 ADDRESSONG MODES…

1. Immediate addressing mode

• The addressing mode in which the data operand is a part of the instruction itself is known
as immediate addressing mode.
• Example: MOV CX, 4929 H,
• ADD AX, 2387 H,
• MOV AL, FFH
2. Register addressing mode
• It means that the register is the source of an operand for an instruction.
• Example: MOV CX, AX ; copies the contents of the 16-bit AX register into the 16-bit CX
register
ADD BX, AX
 ADDRESSING MODES…

3. Direct addressing mode

• The addressing mode in which the effective address of the memory location is written
directly in the instruction.
• Example: MOV AX, [1592H],
MOV AL, [0300H]
4. Register indirect addressing mode
• This addressing mode allows data to be addressed at any memory location through an
offset address held in any of the following registers: BP, BX, DI & SI.
• Example: MOV AX, [BX] ; Suppose the register BX contains 4895H, then the
contents of 4895H are moved to AX
ADD CX, [BX]
 ADDRESSING MODES…

5. Based addressing mode

• In this addressing mode, the offset address of the operand is given by the sum of contents
of the BX/BP registers and 8-bit/16-bit displacement.
• Example: MOV DX, [BX+08],
ADD CL, [BX+16]
6. Indexed addressing mode
• In this addressing mode, the operands offset address is found by adding the contents of SI
or DI register and 8-bit/16-bit displacements.
• Example: MOV BX, [SI+08],
ADD AL, [DI+16]
ADDRESSING MODES…

7. Based-index addressing mode

• In this addressing mode, the offset address of the operand is computed by summing
the base register to the contents of an Index register.
• Example: ADD CX, [BX+SI],
MOV AX, [BX+DI]
8. Based indexed with displacement mode
• In this addressing mode, the operands offset is computed by adding the base register
contents. An Index registers contents and 8 or 16-bit displacement.
• Example: MOV AX, [BX+DI+08],
ADD CX, [BX+SI+16]
 8237 DMA CONTROLLER

• The DMA I/O technique provides direct access to the memory while the
microprocessor is temporarily disabled.
• Disk memory systems and video systems are often DMA-processed.
• Disk memory includes floppy, fixed, and optical disk storage. Video systems
include digital and analog monitors.
• Two control signals are used to request and acknowledge a direct memory access
(DMA) transfer in the microprocessor-based system.
• the HOLD pin is an input used to request a DMA action
• the HLDA pin is an output that acknowledges the DMA action
• Two control signals are used to request and acknowledge a direct memory access
(DMA) transfer in the microprocessor-based system.
 BASIC DMA OPERATION

– HOLD is sampled in any clocking cycle

– when the processor recognizes the hold, it stops executing software and enters
hold cycles
– HOLD input has higher priority than INTR or NMI
– the only microprocessor pin that has a higher priority than a HOLD is the RESET
pin
 DMA OPERATION…
• Direct memory accesses normally occur between an I/O device and memory
without the use of the microprocessor.
•a DMA read transfers data from the memory
to the I/O device
•A DMA write transfers data from an I/O device
to memory
• Memory & I/O are controlled simultaneously.
• which is why the system contains separate memory and I/O control signals
• A DMA read causes the MRDC and IOWC signals to activate simultaneously.
• A DMA write causes the MWTC and IORC signals to both activate.
 DMA CONTROLLER

8086 requires a controller

or circuit such as shown in
Figure for control bus
signal generation.
The DMA controller
provides memory with its
address, and controller
signal (DACK) selects the
I/O device during the
transfer.
 8237 DMA CONTROLLER…

• 8237 is not a discrete component in modern microprocessor-based systems.

• it appears within many system controller chip sets
• 8237 is a four-channel device compatible with 8086/8088, adequate for
small systems.
• expandable to any number of DMA channel inputs
• 8237 is capable of DMA transfers at rates up to 1.6M bytes per second.
• each channel is capable of addressing a full 64K-byte section of memory
and transfer up to 64K bytes with a single programming
 8237 DMA
CONTROLLER PIN
DIAGRAM
 8237 PIN DESCRIPTION…

• DRQ0−DRQ3: These are the four individual channel DMA request inputs, which are
used by the peripheral devices for using DMA services. When the fixed priority
mode is selected, then DRQ0 has the highest priority and DRQ3 has the lowest
priority among them.

• DACKo − DACK3:These are the active-low DMA acknowledge lines, which updates
the requesting peripheral about the status of their request by the CPU. These lines
can also act as strobe lines for the requesting devices.

• Do − D7: These are bidirectional, data lines which are used to interface the system
bus with the internal data bus of DMA controller. In the Slave mode, it carries
 8237 PIN DESCRIPTION…
• IOR: It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8237 in the Slave mode. In the master mode, it is used to read data from
the peripheral devices during a memory write cycle.

• IOW: It is an active low bi-direction tri-state line, which is used to load the contents of the
data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or
terminal count register. In the master mode, it is used to load the data to the peripheral devices
during DMA memory read cycle.

• CLK: It is a clock frequency signal which is required for the internal operation of 8237.

• RESET: This signal is used to RESET the DMA controller by disabling all the DMA channels.
 8237 PIN DESCRIPTION

• Ao - A3
• These are the four least significant address lines. In the slave mode, they act as an input,
which selects one of the registers to be read or written. In the master mode, they are the
four least significant memory address output lines generated by 8237.
• CS
• It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. In the master mode, it disables the read/write operations to/from 8237.
• A4 - A7
• These are the higher nibble of the lower byte address generated by DMA in the master
mode.
 8237 PIN DESCRIPTION
• READY: It is an active-high asynchronous input signal, which makes DMA ready by
inserting wait states.
• HRQ: This signal is used to receive the hold request signal from the output device. In
the slave mode, it is connected with a DRQ input line 8253. In Master mode, it is
connected with HOLD input of the CPU.
• HLDA:It is the hold acknowledgement signal which indicates the DMA controller
that the bus has been granted to the requesting peripheral by the CPU when it is set to
1.
• MEMR:It is the low memory read signal, which is used to read the data from the
addressed memory locations during DMA read cycles.
• MEMW: It is the active-low three state signal which is used to write the data to the
addressed memory location during DMA write operation.
 8237 PIN DESCRIPTION…

• ADSTB: This signal is used to convert the higher byte of the memory address
generated by the DMA controller into the latches.
• AEN: This signal is used to disable the address bus/data bus.
• TC: It stands for ‘Terminal Count’, which indicates the present DMA cycle to the
present peripheral devices.
• MARK: The mark will be activated after each 128 cycles or integral multiples of it
from the beginning. It indicates the current DMA cycle is the 128th cycle since the
previous MARK output to the selected peripheral device.
• Vcc: It is the power signal which is required for the operation of the circuit.
DMA CONTROLLER
SIGNAL DIAGRAM
DMA CONTROLLER
CONNECTION
SCHEME
 DMA CONTROLLER CONNECTION SCHEME…

• Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory,
the device has to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU
to assert the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control bus.
The CPU leaves the control over bus and acknowledges the HOLD request
through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.
PROGRAMMABLE PERIPHERAL INTERFACE
8255(PPI)

• Any application of Microprocessor Based system requires the transfer of

data between external circuitry to the Microprocessor and Microprocessor
to the External circuitry.
• User can give information (i.e. input) to the Microprocessor using
keyboard and user can see the result or output information from the
Microprocessor with the help of display.
• Hence, interfacing is used to exchange information between two different
applications/devices.
8255 PPI INTRODUCTION

• The 8255 is a general-purpose parallel I/O interfacing device designed for

use in Intel microcomputer systems.
• Its function is to interface peripheral equipment to the microcomputer data
bus.
• The functional configuration of the 8255 is programmed by the system
software so that normally no external logic is necessary to interface
peripheral devices or structures.
 8255 PPI

• BLOCK DIAGRAM
 8255 PPI FEATURES

PORT A:
This is an 8-bit buffered I/O latch.
It can be programmed by mode 0 , mode 1, mode 2.
PORT B:
• This is an 8-bit port
• It can be programmed by mode 0 and mode 1.
PORT C:
• This is an 8-bit port
• It is splitted into two parts.
• It can be programmed by bit set/reset operation.
 8255 PPI FEATURES…

Group A and Group B control:

Group A and B get the Control Signal from CPU and send the command to the
individual control blocks.

Group A send the control signal to port A and Port C (Upper) PC7-PC4.

Group B send the control signal to port B and Port C (Lower) PC3-PC0.
8255 PPI FEATURES…

Data Bus buffer:

• It is an 8-bit bidirectional Data bus.

• Used to interface between 8255 data bus with system bus.

• The internal data bus and Outer pins D0-D7 pins are connected in internally.

• The direction of data buffer is decided by Read/Control Logic.

 8255 PPI FEATURES…

Read/Write Control Logic:

• This is getting the input signals from control bus and Address bus

• Control signal are RD’ and WR’.

• Address signals are A0,A1,and CS’.

• 8255 operation is enabled or disabled by CS’.

 8255 PPI

• PIN DIAGRAM
 Function of pins:

Data bus(D0-D7):These are 8-bit bi-directional buses, connected to

microprocessor’s data bus for transferring data.
CS: This is Active Low signal. When it is low, then data is transfer from
microprocessor.
• Read: This is Active Low signal, when it is
Low read operation will be start.
• Write: This is Active Low signal, when it is
Low Write operation will be start.
• Address (A0-A1):This is used to select the
ports as shown in table:
 8255 PPI PINOUT:

• RESET: This is used to reset the device. That means clear control registers.
• PA0-PA7:It is the 8-bit bi-directional I/O pins used to send the data to
peripheral or to receive the data from peripheral.
• PB0-PB7: It is the 8-bit bi-directional I/O pins used to send the data to
peripheral or to receive the data from peripheral
• PC0-PC7:This is also 8-bit bidirectional I/O pins. These lines are divided
into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
 OPERATION MODES:

BIT SET/RESET MODE:

• The PORT C can be Set or Reset by sending OUT instruction to the
CONTROL registers.
I/O MODES:
• MODE 0 (Simple input/Output):
• In this mode , port A, port B and port C is used as individually (Simply).
• Features:
• Outputs are latched , Inputs are buffered not latched.
• Ports do not have Handshake or interrupt capability.
 I/O MODE:

• I/O MODE CONTROL

WORD FORMAT:
• The control word for both
mode is same.
• Bit D7 is used for specifying
whether word loaded into Bit
set/reset mode or Mode
definition word.
• D7=1=Mode definition
mode.
• D7=0=Bit set/Reset mode.
 BSR MODE:

• Bit set/reset control word format:

• PC0-PC7 is set or reset as per the
status of D0.
• A BSR word is written for each bit
• Example:
• PC3 is Set then control register will
be 0XXX0111.
• PC4 is Reset then control register will
be 0XXX01000.
• X is a don’t care.
WRITE A PROGRAM FOR IC 8255 TO READ DIP SWITCHES AND DISPLAY
THE READING FROM PORT B TO PORT A AND FROM PORT 𝐶𝐿 AT PORT 𝐶U?

Port Address:
Since 8255 is memory mapped
I/O, suppose it is addressed at
8000H.
Then when Chip select is
enabled, then port addresses of
8255 will be
Port A- 8000H (A1=0, A0=0)
Port B- 8001H (A1=0, A2=1)
Port C- 8002H (A1=1, A2=0)
Control Register- 8003H
CONTROL WORD:
PROGRAM
MVI A,83H Load accumulator with the control word
STA 8003H Write word in the control register to initialize the ports
LDA 8001H Read switches at Port B
STA 8000H Display the reading at Port A
LDA 8002H Read switches at Port C
ANI 0FH Mask the upper four bits of Port C; these bits are not input data
RLC
RLC
RLC
RLC
STA 8002H Display data at Port 𝐶𝑈
HLT
WRITE A BSR CONTROL WORD TO SET BITS
PC7 AND PC0
WRITE A BSR CONTROL WORD TO SET BITS
PC7 AND PC0

TO SET PC0 CONTROL WORD WILL BE:

PC0=01H
WRITE A BSR CONTROL WORD TO SET BITS
PC7 AND PC0

• MVI A, 0FH Load byte in accumulator to set PC7

• OUT 8003H Set PC7=1
• MVI A, 07H Load byte in accumulator to set PC3
• OUT 8003H Set PC3=1 RET
 8255 PPI OPERATION MODES:

BIT SET/RESET MODE:

• The PORT C can be Set or Reset by sending OUT instruction to the
CONTROL registers.

I/O MODES:
• MODE 0 (Simple input/Output):
• MODE 1 (HANDSHAKE)
• MODE 2 (BIDIRECTIONAL)
 8255 PPI I/O OPERATING MODES

Mode 0 (Basic I/O): Three simple I/O ports.

Ports A and B operate as either inputs or outputs.
Port C is divided into two 4-bit groups either of which can be operated as
inputs or outputs.
MODE 1: (Input/output with
Handshake)
In this mode, input or output is
transferred by hand shaking Signals.
Handshaking signals is used to transfer
data between the devices whose data
transfer speed is not same.
MODE 2: Bi-directional I/O data transfer:

• This mode allows bidirectional data transfer over a single 8-bit data bus
using handshake signals.
• This feature is possible only Group A
• Port A is working as 8-bit bidirectional port.
• PC3-PC7 is used for handshaking purpose.
• The data is sent by CPU through this port when the peripheral request it.
 MODE 0 (Basic I/O):

• This mode provides simple input and output operations for each of the three
ports.
• No handshaking is required, data is simply written to or read from a specific
port.
• The basic features of this mode are:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Input are not latched
MODE 1: (Input/output with Handshake)

• This mode provides a means for transferring I/O data to or from a specified port
in conjunction with strobes or “hand shaking” signals.
• In this mode, port A and port B use the lines on port C to generate or accept
these “hand shaking” signals.
• The basic features of this mode are:
• Two Groups (Group A and Group B).
• Each group contains one 8-bit port and one 4-bit control/data port.
• The 8-bit data port can be either input or output.
• Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit port.
Control signals for input configuration
• STB (Strobe Input).
• A “low” on this input loads data into the input latch.
• IBF (Input Buffer Full F/F)
• A “high” on this output indicates that the data has been loaded into the input latch.
• IBF is set by STB’ input being low and is reset by the rising edge of the RD’ input.
• INTR (Interrupt Request)
• A “high” on this output can be used to interrupt the CPU when and input device is requesting
service.
• INTR is set by the condition: STB is a “one”, IBF is a “one” and INTE is a “one”.
• It is reset by the falling edge of RD.
• This procedure allows an input device to request service from the CPU by simply strobing its
data into the port.
• INTE A: Controlled by bit set/reset of PC4.
• INTE B: Controlled by bit set/reset of PC2.
Control signals for input
configuration
Control signals for output configuration
• OBF - Output Buffer Full :
• The OBF’ output will go “low” to indicate that the CPU has written data out to be specified
port.
• The OBF’ will be set by the rising edge of the WR input and reset by ACK input being low.
• ACK – (Acknowledge Input):
• A “low” on this input informs the 82C55A that the data from Port A or Port B is ready to be
accepted.
• A response from the peripheral device indicating that it is ready to accept data
• INTR - (Interrupt Request):
• A “high” on this output can be used to interrupt the CPU when an output device has accepted
data transmitted by the CPU.
• INTR is set when ACK is a “one”, OBF is a “one” and INTE is a “one”.
• It is reset by the falling edge of WR.
• INTE A: Controlled by bit set/reset of PC6.
• INTE B: Controlled by bit set/reset of PC2.
Control signals for output
configuration
MODE 2: Bi-directional I/O data transfer:

• This mode provides a means for communicating with a peripheral device or

structure on a single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O).
• In this mode, port A uses the lines on port C to generate or accept these “hand
shaking” signals.
• The basic features of this mode are:
• Used in Group A only.
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port C)
• Both inputs and outputs are latched.
• The 5-bit control port (Port C) is used for control and status for the 8-bit,
 MODE 2…
• Input Operations:
• STB’ - (Strobe Input): A “low” on this input loads data into the input latch.
• IBF - (Input Buffer Full F/F): A “high” on this output indicates that data has been loaded
into the input latch.
• INTE 2 - (The INTE flip-flop associated with IBF): Controlled by bit set/reset of PC4.
• INTR - (Interrupt Request): A high on this output can be used to interrupt the CPU for
both input or output operations.
• Output Operations:
• OBF’ - (Output Buffer Full): The OBF output will go “low” to indicate that the CPU has
written data out to port A.
• ACK’ - (Acknowledge): A “low” on this input enables the three-state output buffer of port
A to send out the data. Otherwise, the output buffer will be in the high impedance state.
• INTE 1 - (The INTE flip-flop associated with OBF): Controlled by bit set/reset of PC4.
CONTROL SIGNALS FOR
MODE 2:
PROGRAMMABLE INTERRUPT CONTROLLER
8259 PIC

• The 8259 is known as the Programmable Interrupt Controller (PIC)

microprocessor.
• In 8085 and 8086 there are five hardware interrupts and two hardware
interrupts respectively.
• By adding 8259, we can increase the interrupt handling capability.
• This chip combines the multi-interrupt input source to single interrupt output.
• This provides 8-interrupts from IR0 to IR7.
8259 BLOCK DIAGRAM
 8259 BLOCKS:
• Data Bus Buffer: This block is used to communicate between 8259 and
8085/8086 by acting as buffer. It takes the control word from 8085/8086 and send
it to the 8259. It transfers the opcode of the selected interrupts and address of ISR
to the other connected microprocessor. It can send maximum 8-bit at a time.
• R/W Control Logic: This block works when the value of pin CS is 0. This block
is used to flow the data depending upon the inputs of RD and WR. These are
active low pins for read and write.
• Control Logic: It controls the functionality of each block. It has pin called INTR.
This is connected to other microprocessors for taking the interrupt request. The
INT pin is used to give the output. If 8259 is enabled, and also the interrupt flags
of other microprocessors are high then this causes the value of the output INT pin
high, and in this way this chip can responds requests made by other
 8259 BLOCKS:

• Interrupt Request Register: It stores all interrupt level that are requesting for
interrupt service.
• Interrupt Service Register: It stores interrupt level that are currently being execute.
• Interrupt Mask Register: It stores interrupt level that will be masked, by storing
the masking bits of interrupt level.
• Priority Resolver: It checks all three registers and set the priority of the interrupts.
Interrupt with the highest priority is set in the ISR register. It also reset the interrupt
level which is already been serviced in the IRR.
• Cascade Buffer: To increase number of interrupt pin, we can cascade more number
of pins, by using cascade buffer. When we are going to increase the interrupt
capability, CSA lines are used to control multiple interrupts.
8259 PIN DIAGRAM

• Intel 8259 is designed as a 28-pin-

programmable IC available as a package
named DIP (Dual inline package).
 8259 PINOUT:
• D7-D0: For communication with the processor, there are Eight bi-directional data pins.
• RD*: It is active low-input pin activated by the processor to read the information status from
the 8259.
• WR*: It is an active low-input pin which is activated by the processor to write the control
information to 8259.
• CS*:For selecting the chip it is used an active low input pin.
• A0: An address input pin used along with RD* and WR* which is used to identify the various
command words.
• IR0-IR7: There are Eight asynchronous interrupt request inputs. These interrupt requests can
be programmed for level-trigger or edge-triggered mode.
• INT:A strong active high-output pin which interrupts the processor. Always connected to the
INTR interrupt input of 8085. The INT output is only activated when all the given conditions
 8259 PINOUT:

• INTA’: It is termed as an active low-input pin. The 8259 receives the signal
from INTA* to the output of 8085. 8085 sends the three consecutive INTA*
signals, the 8259sends a 3-byte CALL instruction to the 8085 via D7-0 pins.
The two bytes termed as second and third bytes of the CALL instruction
contains the ISS address which depends on the IR input of 8259 that is going
to be serviced.
• CAS:2-0: These are cascaded lines. Used only when there are multiple 8259s
in the system. The interrupt control system might have a master 8259 and
maximum eight Slave 8259s.
• SP*/EN’: This stands for “slave program/enable buffer”. This pin serves dual
function. When it is used as EN* pin it provides an active low-output pin that
 8259 COMMAND WORDS:

• The 8259A accepts two types of command words generated by the CPU:
• 1. Initialization Command Words (ICWs): Before normal operation can begin, each
8259A in the system must be brought to a starting pointed by a sequence of 2 to 4
bytes timed by WR pulses.
• 2. Operation Command Words (OCWs): These are the command words which
command the 8259A to operate in various interrupt modes. These modes are:
• a. Fully nested mode
• b. Rotating priority mode
• c. Special mask mode
• d. Polled mode
• The OCWs can be written into the 8259A anytime after initialization
COMMAND WORDS:

• Initialization Command Word 1 (ICW1)

• Initialization Command Word 2 (ICW2)
• Initialization Command Word 3 (ICW3)
• Initialization Command Word 4 (ICW4)

• Operation Command Word 1 (OCW 1)

• Operation Command Word 2 (OCW2)
• Operation Command Word 3 (OCW3)
 ICW1:

1.Single or multiple 8259As in

the system
2. 4 or 8 bit interval between the
interrupt vector locations.
3.The address bits A7 – A5 of the
CALL instruction. (3 bits of
lower byte address of CALL are
given by user, rest bits are
inserted by 8259A)
4.Edge triggered or level
triggered interrupts.
5.ICW4 is needed or not.
 ICW2

This is used to
load the high
order byte of the
interrupt vector
address of all the
interrupts.
 ICW3

ICW3 is required
only if there is more
than one 8259 in the
system and if they are
cascaded.
An ICW3 operation
loads a slave register
in the 8259
Programmable
 ICW4:

It specifies,
•Whether to use special fully
nested mode or non-special
fully nested mode.
•Whether to use buffered mode
or non buffered mode.
•Whether to use Automatic
EOI or Normal EOI.
•CPU used, 8086/8088 or 8085.
 8259 COMMAND WORDS

• Once initialization command words are written, 8259 is ready to receive

the interrupts.
• And, OCWs can be used to mask and unmask IR0-IR7 and set their
priority.
OCW1:
OCW1 is used for enabling
or disabling the recognition
of specific interrupt
requests by programming
 OCW2:

The R (Rotate), SL (Select-Level),

EOI bits control the Rotate and
End of Interrupt Modes and
combinations of the two.
L2-L0 are used to specify the
interrupt level to be acted upon
when the SL bit is active.
 OCW3:

OCW3 is used to read the

status of the registers; and to
set or reset the Special Mask
and Polled modes.
 PROGRAMMABLE COMMUNICATION INTERFACE
(8251A)
• 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter)
for serial data communication.
•  It is a programmable peripheral interface designed for synchronous
/asynchronous serial data communication.
•  Serial data transmission is widely used in communications over long distances.
Parallel communication requires many wires to be laid between the two
communicating points. Hence, usually data is converted to serial format and sent
over fewer number of wires to the destination.
•  Receives parallel data from the microprocessor & transmits serial data after
conversion of parallel data to serial data.
•  Also receives serial data from the outside & transmits parallel data to the
microprocessor after conversion of serial data into parallel data.
 SERIAL COMMUNICATION

• The process of sending data bit by bit sequentially, over a single channel between
sender and receiver is known as serial transmission of data.
• • It requires only one communication line rather than n lines to transmit data from
sender to receiver.
• • For correct data transmission, there has to be some form of synchronization
between transmitter and receiver.
• • Serial communication reduce the cost of an IC package by reducing the number of
pins used for communication between different IC’s, instead of using parallel
communication.
SERIAL COMMUNICATION…

• Bit rate: - Number of bits sent every second (BPS)

• Baud rate: - Number of symbols sent every second, where every symbol
can represent more than one bit.
• • The sender and receiver must agree on a set of rules (Protocol) on :
• 1. When data transmission begins and ends.
• 2. The used bit rate and data packaging format.
Types of Transmissions

• SIMPLEX
• HALF DUPLEX
• FULL DUPLEX
SYNCHRONOUS Vs ASYNCHORONOUS
• SYNCHRONOUS DATA TRANSFER:
• • Sender and receiver use the same clock signal
• • Supports high data transfer rate
• • Needs clock signal between the sender and the receiver
• • A master (or one of the senders) should provide the clock signal to all the
receivers in the synchronous data transfer.
• ASYNCHRONOUS DATA TRANSFER:
• • For asynchronous data transfer, there is no common clock signal between the
sender and receivers.
• • Sender provides a synchronization signal to the receiver before starting the
transfer of each message
 SERIAL SYNCHORONOUS TRANSMISSION
• Synchronous Transmission is efficient, reliable and is used for transferring a large
amount of data.
• Communication is performed is based on a synchronization signal added to each bit
from the sending side.
• Synchronization between the source and target is required so that the source knows
where the new byte begins since there is no space between the data.
• It provides real-time communication between connected devices. Chat Rooms, Video
Conferencing, telephonic conversations, as well as face to face interactions, are some of
the examples of Synchronous Transmission
 ASYNCHORONOUS TRANSMISSION
• In Asynchronous Transmission data flows as 1 byte or a character at a time.
• For asynchronous transmission, a start bit is used to identify the beginning of each character
and at least one stop bit is used to identify end of data character, this is known as bit
synchronization.
• Effectively, the sender and receiver are synchronized on a character by character basis.
• Asynchronous serial data communication is widely used for character-oriented transmissions,
while block-oriented data transfers use the synchronous method.
• In the asynchronous method, each character is placed between start and stop bits. This is
called framing.
8251 PIN DIAGRAM:
 8251 PINOUT:
 CS’ – Chip Select : When signal goes low, the 8251A is selected by the MPU for
communication.
 C/D’ – Control/Data : When signal is high, the control or status register is addressed;
when it is low, data buffer is addressed. (Control register & status register are
differentiated by WR and RD signals)
 WR’ : When signal is low, the MPU either writes in the control register or sends
output to the data buffer.
 RD’ : When signal goes low, the MPU either reads a status from the status register
or accepts data from data buffer.
 RESET : A high on this signal reset 8251A & forces it into the idle mode.
 CLK : Clock input, usually connected to the system clock for communication with
 8251 PINOUT…

• TxD-(Transmit Data):-This is an output line for transmitting serial bits out on the
falling edge of TxC, which transmitter clock.
• TxC-(Transmitter clock):-This input signal controls the rate at which the bits are
transmitted by the USART. In synchronous mode, the baud rate will be the same as
the frequency of TxC. In asynchronous mode, it is possible to select the baud rate
factor by mode instruction.
• TxRDY-Transmitter Ready: This is the output signal. When it is high, it indicates the
buffer register is empty and USART is ready to accept a byte. It can be used either to
interrupt the MPU or to indicate the status. This signal is reset when a data byte is
loaded into the buffer.
• TxE-Transmitter Empty: This is an output signal. Logic 1 on this indicates the
output register is empty after transmitting all the characters. This signal is reset when
 8251 PINOUT…

• RxD-Receive Data: Bits are received serially on this line and converted into a
parallel byte in the receiver input register.
• RxC-Receiver clock: This is a clock signal that controls the rate at which bits are
received by the USART. In the asynchronous mode, the clock can be set to 1,16
or 64 times the baud.
• RxRDY-Receiver Ready: This is an output signal. It goes high when the USART
has a character in the buffer register and is ready to transfer into the MPU.
• This line can be used either to indicate the status or to interrupt the MPU. When
MPU reads a data character, RxRDY will be reset by the leading edge of RD
signal.
 8251 PINOUT…

• SYNDET/BD (Input or output terminal)

• This pin is used in synchronous mode as SYNDET for detection of synchronous
characters and may be used as either input or output.
• When used as an input (external sync detect mode) a positive signal on syndet/bd
will cause the 8251A to start receiving data characters on the rising edge of the next
RXC.
•When used as output (internal sync detect mode) then syndet pin go high to
indicate that the 8251 has located the sync character.
• In asynchronous mode this pin goes high if receiver line stays low for more than 2
character times. It then indicates a break in the data stream, so used as BD.
BLOCK DIAGRAM

 Data Bus buffer

 Read/Write Control
Logic
 Modem Control
 Transmitter
 Receiver
 8251 BLOCKS:

• Data Bus Buffer: D0-D7 : 8-bit data bus used to read or write status, command
word or data from or to the 8251A.

• Read/Write Control logic: Includes a control logic, six input signals & three
buffer registers:
• Data register
• Control register
• Status register.
• Control logic : Interfaces the chip with MPU, determines the functions of the chip
according to the control word in the control register & monitors the data flow.
 DATA REGISTER

• Data register: Used as an input and output port when the C/D is
low
 CONTROL REGISTER & STATUS REGISTER

CONTROL REGISTER: 16-bit register for a control word consist of two

independent bytes namely mode word & command word.
 Mode word : Specifies the general characteristics of operation such as baud,
parity, number of bits etc.
 Command word : Enables the data transmission and reception.
 Register can be accessed as an output port when the Control/Data pin is
high.
STATUS REGISTER: Checks the ready status of the peripheral.
• Status word in the status register provides the information concerning register
status and transmission errors.
MODEM CONTROL DSR - Data Set Ready : Checks if the Data
Set is ready when communicating with a
modem.
The Pin Diagram of 8251
Microcontroller has a set of control DTR - Data Terminal Ready : Indicates that
inputs and outputs that can be used to the device is ready to accept data when the
simplify the interface to MODEM.
8251 is communicating with a modem.
The MODEM control unit allows to
interface a MODEM to 8251 and to CTS - Clear to Send : If its low, the 8251A
establish data communication though is enabled to transmit the serial data
MODEM over telephone lines. provided the enable bit in the command byte
This unit take care of handshaking is set to ‘1’.
signals for MODEM interface. RTS - Request to Send Data : Low signal
indicates the modem that the receiver is
ready to receive a data byte from the
modem.
TRANSMITTER SECTION

 Accepts parallel data from MPU &

converts them into serial data.
 Has two registers:
 Buffer register : To hold eight bits
 Output register : To convert eight bits
into a stream of serial bits.
 The MPU writes a byte in the buffer
register.
 Whenever the output register is empty;
the contents of buffer register are
transferred to output register.
 TRANSMITTER SECTION

 Transmitter section consists of three output & one input signals

 TxD - Transmitted Data Output : Output signal to transmit the data to
peripherals

 TxC - Transmitter Clock Input : Input signal, controls the rate of

transmission.

 TxRDY - Transmitter Ready : Output signal, indicates the buffer register

is empty and the USART is ready to accept the next data byte.
 RECEIVER SECTION

 Accepts serial data on the RxD pin and converts them to parallel data. It has two registers :
 Receiver input register
 Buffer register
 When RxD goes low, the control logic assumes it is a start bit, waits for half bit time, and
samples the line again. If the line is still low, the input register accepts the following data,
and loads it into buffer register at the rate determined by the receiver clock.
 RxRDY - Receiver Ready Output: Output signal, goes high when the USART has a
character in the buffer register & is ready to transfer it to the MPU.
 RxD - Receive Data Input : Bits are received serially on this line & converted into a parallel
byte in the receiver input register.
 RxC - Receiver Clock Input : Clock signal that controls the rate at which bits are received
by the USART.
RECEIVER SECTION
MODE INSTRUCTION FORMAT
COMMAND INSTRUCTION FORMAT
INTERFACING

• The C/D’  pin is used to select

either control register or data
register. This pin is connected to
the A0 pin of 8085.
• The CS pin of 8251 is attached to
the output of an address decoder
circuit.
• The address decoder uses A7 to
A1 lines of the microprocessor.
• In this diagram the CS will be
enabled when A7 and A4 is at logic
1, and all other lines are at logic 0.
 A0 RD WR Task Port
Address

• From the following 0 0 1 Read Data Word 90H

table, it can be seen
how to read or write
data word, read the 0 1 0 Write Data Word 90H
status word and write
control word. 1 0 1 Read Status Word 91H

1 1 0 Write Control Word 91H

 RS-232 SERIAL INTERFACE

• RS232 defines the signals connecting between DTE and DCE.

• Here, DTE stands for Data Terminal Equipment and an example for DTE is a computer.
• DCE stands for Data Communication Equipment or Data Circuit Terminating
Equipment and an example for DCE is a modem.
• RS232 was introduced in 1960’s and was originally known as EIA Recommended
Standard 232.
• RS232 is one of the oldest serial communication standards with ensured simple
connectivity and compatibility across different manufacturers.
• Originally, the DTEs in RS32 are electromechanical typewriters and DCEs are modems.
RS232 INTERFACE
RS-232…

• RS232 follows asynchronous communication protocol i.e. there is no

clock signal to synchronize transmitter and receiver. Hence, it uses start
and stop bits to inform the receiver when to check for data.
• But the main drawback of RS232 standard is data rate and length of cable.
RS232 supports a maximum baud rate of 19200 bps and the maximum
length of the cable is 20 meters.
DB-9 CONNECTOR:
DB-25 CONNECTOR
DB-25 PIN ASSIGNMENT:
RS-232 APPLICATIONS

• Though RS232 is a very famous serial communication protocol, it is now

has been replaced with advanced protocols like USB.
• Previously they we used for serial terminals like Mouse, Modem etc.
• But, RS232 is still being used in some Servo Controllers, CNC Machines,
PLC machines and some microcontroller boards use RS232 Protocol.
8253/54- Programmable Interval Timers

• Designed for microprocessors to perform timing and counting functions using

three 16-bit registers.

• Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output.

• To operate a counter, a 16-bit count is loaded in its register.

• On command, it begins to decrement the count until it reaches 0, then it

generates a pulse that can be used to interrupt the CPU.
8253 Vs 8254
 FEATURES

The most prominent features of 8253/54 are as follows :

• It has three independent 16-bit down counters.
• It can handle inputs from DC to 10 MHz.
• These three counters can be programmed for either binary or BCD count.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows
the user to check the count value, the programmed mode, the current mode,
and the current status of the counter.
 ARCHITECTURAL BLOCK
DIAGRAM:

n the above figure, there

are three counters, a data
bus buffer, Read/Write
control logic, and a
control register. Each
counter has two input
signals - CLOCK &
GATE, and one output
signal - OUT.
 BLOCKS:
• Data Bus Buffer: It is a tri-state, bi-directional, 8-bit buffer, which is used to
interface the 8253/54 to the system data bus. It has three basic functions −
• Programming the modes of 8253/54.
• Loading the count registers.
• Reading the count values.
• Read/Write Logic: It includes 5 signals, i.e. RD’, WR’, CS’, and the address lines
A0 & A1. In the peripheral I/O mode, the RD’ and WR’ signals are connected to IOR
and IOW, respectively. In the memory mapped I/O mode, these are connected to
MEMR and MEMW.
• Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54,
and CS’ is tied to a decoded address. The control word register and counters are
Control Word Register

This register is accessed when

lines A0 & A1 are at logic 1.
It is used to write a command
word, which specifies the
counter to be used, its mode, and
either a read or write operation.
Following table shows the result
for various control inputs
BLOCKS…

• Counters:
• Each counter consists of a single, 16 bit-down counter, which can be
operated in either binary or BCD.
• Its input and output is configured by the selection of modes stored in
the control word register.
• The programmer can read the contents of any of the three counters
without disturbing the actual count in process.
PIN DIAGRAM
CONTROL WORD
REGISTER AND
COUNTERS SELECTION
MODES OF OPERATION:

• MODE 0 : INTERRUPT ON TERMINAL COUNT

• MODE 1 : HARDWARE-RETRIGGERABLE ONE-SHOT
• MODE 2 : RATE GENERATOR CLOCK
• MODE 3 : SQUARE WAVE GENERATOR
• MODE 4 : SOFTWARE TRIGGERED STROBE
• MODE 5 : HARWARE TRIGGERED STROBE
 MODE 0 : INTERRUPT ON TERMINAL
COUNT

• It is used to generate an interrupt to the microprocessor after a certain interval.

• Initially the output is low after the mode is set. The output remains LOW after
the count value is loaded into the counter.
• The process of decrementing the counter continues till the terminal count is
reached, i.e., the count become zero and the output goes HIGH and will remain
high until it reloads a new count.
• The GATE signal is high for normal counting. When GATE goes low, counting
is terminated and the current count is latched till the GATE goes high again.
MODE 1 : HARDWARE-RETRIGGERABLE ONE-SHOT

• It can be used as a mono stable multi-vibrator.

• The gate input is used as a trigger input in this mode.
• The output remains high until the count is loaded and a trigger
is applied.
MODE 2 : RATE GENERATOR CLOCK

• The output is normally high after initialization.

• Whenever the count becomes zero, another low pulse is generated at the
output and the counter will be reloaded.
MODE 3 : SQUARE WAVE GENERATOR

• This mode is similar to Mode 2 except the output remains low for half of
the timer period and high for the other half of the period.
 Mode 4 − Software Triggered Mode

• In this mode, the output will remain high until the timer has counted to
zero, at which point the output will pulse low and then go high again.
• The count is latched when the GATE signal goes LOW.
• On the terminal count, the output goes low for one clock cycle then goes
HIGH. This low pulse can be used as a strobe.
MODE 5 : HARWARE TRIGGERED STROBE

• This mode generates a strobe in response to an externally generated signal.

• This mode is similar to mode 4 except that the counting is initiated by a
signal at the gate input, which means it is hardware triggered instead of
software triggered.
• After it is initialized, the output goes high.
• When the terminal count is reached, the output goes low for one clock
cycle.
 READ BACK COMMAND FORMAT:

• This feature available only in 8254 and not in 8253.

• Allows user to check the count value, Programmed mode and the current
states of the OUT Pin.
PREVIOUS YEARS QUESTION PAPERS
THE END