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Presentation of Computer Architecture

The document discusses instruction pipelining in computer architecture. It describes instruction pipelining as a technique where the execution of instructions is overlapped by dividing the instruction execution process into stages. This improves processor throughput. However, hazards can occur when instructions interact in unexpected ways, including resource hazards when instructions compete for resources, data hazards due to data dependencies between instructions, and control hazards from branch mispredictions. Solutions to these hazards involve stalling the pipeline as needed.

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Roohul Bayan
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65 views

Presentation of Computer Architecture

The document discusses instruction pipelining in computer architecture. It describes instruction pipelining as a technique where the execution of instructions is overlapped by dividing the instruction execution process into stages. This improves processor throughput. However, hazards can occur when instructions interact in unexpected ways, including resource hazards when instructions compete for resources, data hazards due to data dependencies between instructions, and control hazards from branch mispredictions. Solutions to these hazards involve stalling the pipeline as needed.

Uploaded by

Roohul Bayan
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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COMPUTER ARCHITECTURE

COURSE CODE :3416

• PROCESSOR ORGANIZATION
• INSTRUCTIONS PIPELINING

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INSTRUCTIONS PIPLING

Instruction pipelining is a technique of organizing the


instructions for execution in such a way that the execution of
the current instruction is overlapped by the execution of its
subsequent instruction. Instruction pipelining improves the
performance of the processor by increasing its throughput i.e.
number of instructions per unit time.
In this context, we will discuss the instruction pipelining, how
it works along with the pipelining hazards. We will also
discuss some advantages of instruction pipelining.

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Content used in the Instruction Pipelining in Computer
Architecture

1. Instruction Pipelining
2. Instruction Pipelining Hazardous
3. Advantages of Instruction Pipelining
4. Key Takeaways

 Instruction Pipelining:
Instruction pipelining is a technique of organizing the instructions for execution in such a
way that the execution of the current instruction is overlapped by the execution of its
subsequent instruction. Instruction pipelining improves the performance of the processor
by increasing its throughput i.e. number of instructions per unit time.
 Stages of Instruction Piplining:
 Instruction fetches: Fetch the instruction from the main memory or cache.
 instruction decoding: The processor interprets instruction and determines the operation
that has to be performed.
 Operand fetch: If the execution of the instruction requires operand then the processor
fetches operand from the main memory or cache.
 Instruction Execution: The processor performs the desired operation.
 Operand Store: The result of execution is stored.

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The following figure shows the sequential execution of
Instructions

Figure.

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 Instruction Pipelining Hazardous:
The instruction pipelining hazards is a condition where the
execution of the pipelined instructions is stopped or
delayed, it is also called a pipeline bubble.

Kinds of instruction pipelining hazards.


There are three kinds of instruction pipeline hazards.
 Resource Hazards: When two pipelined instructions or even more,
want to access the same resource it results in resource hazards. It is
also termed structural hazards.
Solution of Resourse Hazards: A solution to this hazard is that
these instructions must be executed serially up to some
portion of the pipeline. Let us understand this with the help of an
example. Consider the main memory you have has a single port that
restricts the processor to perform instruction fetch, read data and write
data one at a time. This means you cannot perform the operand read &
write operation, from memory in parallel with instruction fetch.
Now consider that there are three instructions in the pipeline. So in the
normal conditions, the operand fetch of instruction 1 must-have
overlapped the instruction fetch of instruction 3. But there is a case
that source operand of instruction 1 is present in main memory instead
of register and the rest of all the operands are in register. So we would
halt the instruction fetch of instruction 3 for one clock cycle. Because
instruction 1 will fetch its source operand from memory so in the same
clock cycle instruction 3 cannot perform instruction fetch in parallel to Prep.by Roqia bibi & Ritaj Fati ma
operand fetch of instruction 1
FIGURE OF THE RESOURSE HAZARDS

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 Data Hazards: The data hazard is a condition when accessing an
operand location creates conflict

Consider that you have two instructions:


ADD R1, R2, R3
SUB A, R1
Solution of Data Hazards: Observe the instructions above the result of
add instruction is stored in register R1 after the execution. This R1 act
as an operand for subtract instruction. Now in the figure below notice
that the register R1 is updated with the add result in clock cycle t 4. But
the subtract instruction need its operand R1 at the t 3 clock cycle. But if
subtract instruction fetches the operand R1 in the t 3 clock cycle then it
will generate an incorrect result.
So the subtract instruction must stall or halt for two clock cycles
because for the correct result the subtract instruction is dependent on
the result of add instruction. This dependency is also called data
dependency.

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Figure

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 Control Hazards:

Control hazards occur when instruction pipelining fails in predicting


branches in the instruction.
Solution of the Control Hazards: Let us understand this with the help of
an example. Consider the first instruction I1 in the pipeline is a branch
instruction that targets instruction I6.
The instruction I1 is fetched in cycle t0, decoded in cycle t1, fetch
operands in cycle t2 and perform execution in cycle t3 where the target
address is computed. But till then three instructions I 2, I3 and I4 are
pipelined in cycle t1, t2 and t3 which must be discarded as instruction I1 is
branch instruction which will compel the processor to execute the
instruction I9 after instruction I1.
This is how control hazards lead to delay of three cycles t 1, t2 and
t3 between I1 and I 6 which is also termed as branch delay.
This branch delay could be minimized if the branches in the instruction
could be predicted at the decoding stage only.

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FIGURE
Control Hazards

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PRESENTED & SUBMITTED TO :
Honorable Sir: Eng.Umair Hafeez Khan

PRESENTED & SUBMITTED BY:


ROQIA BIBI & RITAJ FATIMA

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