Basic Processing Unit

Processing Unit
• A processor is responsible for reading program
instructions from the computer’s memory and
executing them.
• It fetches one instruction at a time.
• It decodes (interprets) the instruction.
• Then, it carries out the actions specified.
 Some Fundamental Concepts
• Consider a 32-bit computer in which each instruction is contained in
one word in the memory ( RISC-style instruction set architecture)
To execute an instruction, the processor has to perform the following
steps:
1. Fetch the contents of the memory location pointed to by the PC.
The contents of this location are the instruction to be executed; hence
they are loaded into the IR. In register transfer notation, the required
action is IR←[[PC]]
2. Increment the PC to point to the next instruction. Assuming that the
memory is byte addressable, the PC is incremented by 4; that is
PC←[PC] + 4
3. Carry out the operation specified by the instruction in the IR.
 Hardware Components of a Processor

• PC provides
instruction address.
• Instruction is fetched
into IR
• Instruction address
generator updates PC
• Control circuitry
interprets instruction
and generates control
signals to perform the
actions needed.
 Data Processing Hardware

• A typical computation operates on data stored in registers.

Contents of register A are processed and deposited in register
B.
• These data are processed by combinational circuits, such as
adders, and the results are placed into a register.
 Data Processing Hardware
• A clock signal is used to control the timing of
data transfers. The registers comprise edge-
triggered flip-flops into which new data are
loaded at the active edge of the clock.
• Assume that the rising edge of the clock is the
active edge. The clock period, which is the time
between two successive rising edges, must be
long enough to allow the combinational circuit
to produce the correct result.
 A multi-stage digital processing system
• Operation is often be broken down into several simpler steps,
where each step is performed by a subcircuit of the original circuit.
• These subcircuits can then be cascaded into a multistage
structure .
• Then, if n stages are used, the operation will be completed in n
clock cycles.
• Since these combinational subcircuits are smaller, they can
complete their operation in less time, and hence a shorter clock
period can be used.
• A key advantage of the multi-stage structure is that it is suitable
for pipelined operation,
A multi-stage digital processing system
 Why multi-stage?
• Processing moves from one stage to the next in
each clock cycle.
• Such a multi-stage system is known as a pipeline.
• High-performance processors have a pipelined
organization.
• Pipelining enables the execution of successive
instructions to be overlapped.
• Pipelining will be discussed later.
 Instruction execution
Consider the instruction Load R5, X(R7)
Execution of this instruction involves the following actions:
• Fetch the instruction from the memory.
• Increment the program counter.
• Decode the instruction to determine the operation to be performed.
• Read register R7.
• Add the immediate value X to the contents of R7.
• Use the sum X + [R7] as the effective address of the source operand, and
read the contents of that location in the memory.
• Load the data received from the memory into the destination register, R5.
 Instruction execution
Fetching and executing the Load R5, X(R7) instruction
can be completed as follows:
1. Fetch the instruction and increment the program
counter.
2. Decode the instruction and read the contents of
register R7 in the register file.
3. Compute the effective address: X + [R7]
4. Read the memory source operand.
5. Load the operand into the destination register, R5.
 Instruction execution
Arithmetic and Logic Instructions
• Instructions that involve an arithmetic or logic operation
can be executed using similar steps. They differ from the
Load instruction in two ways:
• There are either two source registers, or a source
register and an immediate source operand.
• No access to memory operands is required.
A typical instruction of this type is
Add R3, R4, R5
Add R3, R4,#50
 Instruction execution
Arithmetic and Logic Instructions
Add R3, R4, R5
It requires the following steps:
1. Fetch the instruction and increment the program
counter.
2. Decode the instruction and read the contents of
source registers R4 and R5.
3. Compute the sum [R4] + [R5].
4. Load the result into the destination register, R3.
 Instruction execution
All instructions converted to 5 steps so that the same 5 stage pipeline can
be used to execute all instructions
Arithmetic and Logic Instructions
Add R3, R4, R5
It requires the following steps:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read the contents of source registers R4 and
R5.
3. Compute the sum [R4] + [R5].
4. No action.
5. Load the result into the destination register, R3.
 Instruction execution
Arithmetic and Logic Instructions
If the instruction uses an immediate operand, as in
Add R3, R4, #1000
• the immediate value is given in the instruction word. Once the
instruction is loaded into the IR, the immediate value is
available for use in the addition operation.
The same five-step sequence can be used, with steps 2 and 3
modified as:
2. Decode the instruction and read register R4.
3. Compute the sum [R4] + 1000.
 Instruction execution
Store R6, X(R8)
stores the contents of register R6 into memory location X + [R8].
It can be implemented as follows:
1. Fetch the instruction and increment the program counter.
2. Decode the instruction and read registers R6 and R8.
3. Compute the effective address X + [R8].
4. Store the contents of register R6 into memory location X +
[R8].
5. No action.
Five-step sequence of actions to fetch and execute
an instruction.

1.Fetch an instruction and increment the program

counter.
2. Decode the instruction and read registers from the
register file.
3. Perform an ALU operation.
4. Read or write memory data if the instruction involves
a memory operand.
5. Write the result into the destination register, if
needed.
END