PLACEMENT

Presentation by
SUDHIR KUMAR MADHI
 Placement
• Placement
• In this stage, all the standard cells are placed in the design (size, shape & macro-
placement is done in floor-plan). Placement will be driven by different criteria like timing
driven, congestion driven, power optimization etc. Timing & Routing convergence
depends a lot on quality of placement. Different tasks in placement are listed below;
1.Pre-placement
2.Initial placement (Coarse placement)
3.Legalizations
4.Removing existing buffer trees
5.High Fan-out Net Synthesis (HFNS)
6.Iterations of timing/power optimizations [cell sizing, moving, net spitting, gate cloning,
buffer insertion, area recovery]
7.Area recovery
8.Scan-chain re-ordering
9.TIE cell insertions
 checks before doing placement:
• After completion of floorplanning, power planning and
placement of physical only cells Endcap cells and Tap cells, we
check the base DRC and errors related to floorplanning like
vertical spacing error, horizontal spacing error, min site row,
vertical site row, and alignment.
• After inserting the tap cells, check to ensure that a standard cell
peaceable area is protected by tap cells. Tap cells are placed
correctly or not.
 checks before doing placement:
•  Tap cells are typically used when most or all of the standard
cells in the library contains no substrate or well taps. Generally,
the design rule specifies the maximum distance allowed between
every transistor in a standard cells and a well or substrate tap.
• Advanced nodes often requires the insertion of additional tap
cells to manage the substrate and well noise. Before placing the
standard cells we add boundary cells (Endcap cells) also, which
are added to the ends of the cell rows and around the boundaries
of objects such as core and hard macros and we checked that
endcap cells are placed or not.
 checks before doing placement:
• After you have done the floorplanning i.e. created the core area,
placed the macros and decided the power network structure of
your design, it is time to let the tool do standard cell placement. 
 PLACEMENT
• Placement is the process of finding a suitable physical location
for each cell in the block. Tool only determine the location of
each standard cell on the die.
• Placement does not just place the standard cell available in the
synthesized netlist, it also optimized the design
• The tool determines the location of each of the standard cell on
the core. Various factors come into play like the timing
requirement of the system, the interconnect length and hence
the connections between cells, power dissipation, etc.
• placement solution used, and it is very important in determining
the performance of the system as the geometries shrink.
• Placement will be driven based on different criteria like timing
driven, congestion driven, power optimization.
• Placement is performed in two stages: coarse placement and
legalization.
 Goal of placement:
• Timing, power, area optimization
• Routable design
• Minimum cell density and pin density(Reduce the congestion 
due to cells and pins) congestion hot-spots
• Minimum timing DRC’s
• Before starting the placement optimization, it’s always good
practice to do some analyses & checks on the design & tool
settings. This would definitely help in design converge & reduce
iterations.
Inputs and output of placement:
Inputs
Netlist
Floorplan def
Logical and physical library
Design constraint
Technology file

Output:
Placement def
• Before the start of placement optimization all wire load models
are removed. Placement uses RC values from the virtual route to
calculate timing. The virtual route is the shortest Manhattan
distance between two pins. Virtual route RC values are more
accurate than WLM RC’s.
 Coarse placement:
• During the coarse placement, the tool determines an
approximate location for each cell according to the timing,
congestion and multi-voltage constraints. The placed cells don’t
fall on the placement grid and might overlap each other. Large
cells like RAM and IP blocks act as placement blockages for
standard cells. Coarse placement is fast and sufficiently accurate
for initial timing and congestion analysis.
Coarse placement:
 Legalization:
• During legalization, the tool moves the cells to legal locations on
the placement grid and eliminate any overlap between cells.
These small changes to cell location cause the lengths of the
wire connections to change, possibly causing new timing
violations. Such violations can often be fixed by incremental
optimization, for example: by resizing the driving cells.
Legalization:
 Legalization:
• Placement constraints provide guidance during placement and
placement optimization and legalization so that congestion and
timing violations will be reduced.
• 1.       Placement blockages
• 2.      Placement bounds
• 3.      Density constraint
• 4.      Cell spacing constraint
 Placement blockages:

• It is the area where the cells must avoid during placement,

optimization and legalization.
• It can be hard and soft.
• ICC tools supports two types of placement blockage
• Keep-out margin
• Area-based placement blockage: soft, hard, partial
 Keep-out margin: 
• it is a region around the boundary of fixed cells in a block in
which no other cells are placed. The width of the keep-out
margin on each side of the fixed cell can be the same or
different. Keeping the placement of cells out of such regions
avoids congestion and net detouring and produces better QOR
(quality of results).
• Create_keepout_margin –outer {10 10 10 10} my_lib_macro
• Create_keepout_margin –outer {10 10 10 10} my_lib_macro –
type hard –name xyz
Keep-out margin: 
Area-based placement blockage:
• It is a rectangular region in which cells can be placed or not or
we can limit the number of cells.
• Hard blockages: It prevents the placement of standard cells
being placed in the blockage area.
• Create_placement_blockage -boundary {10 20 100 200} –name
pb0. By default it is hard blockages.
• Soft blockage: during optimization buffer/inv can be placed in
that blockage area.
• Create_placement_blockage  -boundary {10 20 100 200} –
name pb1 –type soft
• Partial placement blockages: it limits the cell density in a
particular region.
• Create_placement_blockage –boundary {10 20 100 200} –type
partial –blocked_percentage 40 (it means 40 % area is blocked
for placement of standard cells and rest of the 60% available for
placement of standard cells )
• Note: if you have both blockages are present at the same place
then hard blockages take priority over the soft placement
blockages.
• Placement bounds:It is a constraint that controls the placement
of groups of leaf cells and hierarchical cells. It allows you to group
cells to minimize wire length and place the cells at most
appropriate locations. When our timing is critical during
placement then we create bounds in that area where two
communicating cells are sitting far from another.
• It is a fixed region in which we placed a set of cells. It comprises
of one or more rectangular or rectilinear shapes which can be
abutted or disjoint. In general we specify the cells and ports to be
included in the bound. If a hierarchical cell is included, all cells in
the sub-design belong to the bound.
 Types of bounds:

1.Soft move bound

2.Hard move bound
3.Exclusive move bound
Soft move bound:In this tool tries to place the cells in the move
bound within a specified region, however, there is no guarantee
that the cells are placed inside the bounds.
Create bound –name b0 –type soft –boundary {10 10 20 20}
instance_1 #define softbound for instance_1 with its left corner at
(10 10) and its upper-right corner at (20 20).
• Hard move bound:In this tool must place the cells in the move
bound within a specified region.
Create bound –name b1 –type soft –boundary {10 10 20 20}
instance_2
Exclusive move bound:In this tool tries to place the cells in the
group bound within a floating region, however, there is no
guarantee that the cells are placed inside the bounds
Density controls:It means how the density of cells can be packed.
We can control the overall placement density for the block or the
cell density for specific regions. To control the cell density for
specific regions we can also use partial placement blockages.
 Power optimization:
• Dynamic power: This is the energy dissipated due to the
voltage or logic transitions in the design objects, such as cells,
pins and nets. The dynamic power consumption is directly
proportional to the number and frequency of transition in the
design.
 Static (leakage) power: 
• This is the energy dissipated even when there is no transition in
the circuit? This is also known as leakage power and depends
upon device characteristics. The main contributor to the leakage
power is the sub-threshold-voltage leakage in the device. At
lower technology nodes, leakage power consumption
contributes significantly to the total power consumption of the
circuit
• In a library contains multiple-threshold- voltage cells
• The LVT cells have higher leakage current but better performance.
• The HVT cells have lower leakage current but worst performance.
• Percentage low threshold voltage optimization tries to find a
balance between power and performance goals restricted the use
of LVT cells.
• During low power placement, the tool tries to minimize the length
of high switching nets to improve the power QOR.
• During Dynamic power-driven placement, the tool tries to improve
both the timing and power of the critical nets and the power QOR
without affecting the timing QOR.
 Via ladder insertion:
• A via ladder is a stacked via that starts from the pin layer and
extends into an upper layer where the router connects to it. Via
ladder reduces the via resistance which can improve the
performance and Electromigration robustness. The tool can
automatically insert the via ladder for cell pins on timing critical
paths.
• After initial placement and optimization by using place_opt
command we perform incremental placement and optimization
by using refine_opt command.
 Place_opt: 
• This command performs coarse placement, HFNS, optimization
and legalization. In the place_opt command, the –
congestion option causes the tool to apply –high effort to
congestion removal for better routability, this will require more
runtime and cause area utilization to be less uniform across the
available placement area.
 Refine_opt
• If congestion is found to be a problem after placement and optimization. It
can improve incrementally with the refine_opt command. 
• perform 5 stages
1. Initial path optimization: it incrementally moves registers along
timing paths to improve timing.
2. Incremental placement: to reduce congestion and improve
routability.
3. Incremental optimization: perform incremental timing, area,
congestion and leakage power optimization.
4. Final placement: final phase of path optimization to improve timing
5. Legalization:  tool legalize the placement.
 Magnet placement:
• To improve congestion for a complex floorplan or to improve
timing for the design we can use magnet placement to specify
fixed object as a magnet and have the tool place all the standard
cells connected to the magnet object close to it. We can fix
macrocells, pins of fixed macro or IO ports as the magnet object.
• For best results perform magnet placement before standard cell
placement.
• Command: magnet_placement
• Timing driven placement: Tool tries to place the standard
cells along timing critical path close together to reduce net RC and
meet setup timing
• Congestion driven placement: Tool tries to spread the cells
where the density of cells are more for the reduction of
congestion.
• Different task during placement:
• Placement of standard cells
• Optimization of area, power, congestion and timing.
• Legalization
• HFNS
• Scan chain reordering
 High Fan-out Net Synthesis
(HFNS):
• In the placement stage we do this process. The process of
buffering the high fan-out to balance the load because if design
has too many loads then it affects delay and transition time. We
know delay is load is directly proportional to the delay. By
buffering the HFN the load can be balanced and this process is
called the HFNS.
• High fanout nets are mainly reset, preset, scan enable etc. these
nets are not synthesized in the synthesis stage, also make sure
you set an appropriate fan-out limit for your library using the
command set_max_fanout 20 [design_name]
 Used ideal clock in placement
stage:
• Clock net is also a high fan-out nets but in placement stage we
set set_ideal_clock or set_dont_touch commands on the clock
signal. If we don’t take the ideal clock here the clock constraints
like skew, insertion delay of clock buffers are not used and it
affects the clock tree building. The clock network is ideal and
does not have a clock buffer tree available for accurate clock
network timing analysis. In ICC we use the following command
to make sure that the clock is ideal not propagated in the
placement stage.
• Set_ideal_network [all_fanout –flat –clock_tree]
 DFT optimization:
• If block contains scan chains by default create_placement,
place_opt and clock_opt commands perform DFT optimization.
During initial placement, the tool focuses on the QOR for the
function nets by ignoring the scan chains. After initial
placement, the tool further improves the QOR by repartitioning
and reordering the scan chains based on the initial placement.
• Scan chains reordering reduces wire length so timing will
improve.
• Scan chains reordering minimize congestions and improves
routability
 DFT optimization:
• The scan chain information (SCANDEF) from synthesis can be
transferred to ICC compiler into two ways:
• By loading the netlist in DDC format
• By loading a SCANDEF file.
 TIE cells insertion:
• Sometimes in the netlist some unused inputs are tied to
VDD/VSS (logic1/logic0). It is not recommended to connect a
gate directly to the power network, so we use TIEHI or TIELO
cells if available in the library. These are single pin cells that
effectively ties the pin it connects high or low.
 Optimization techniques:

Netlist constructing only changes existing gates, does not change functionality.
1.Cloning
2.Duplicates gates
3.Gate sizing
4.Swapping of pins that can change the final delay
5.Fan-out splitting
 Congestion:
Congestion occurs when the number of available routing
resources is less than the required routing resources. This
condition we can see in global routing. A congestion map can help
us to visualize the quality of placement. The congestion map
shows the borders between global routing cells highlighted with
different colors that represent the different levels of overflow. The
overflow and underflow of the all selected layers. For example, if
a highlighted light blue on the edge global routing cells shows
10/9 that means there are 9 available wire tracks and the required
tracks are 10.
 What are the reasons for
congestion?
• High standard cell density in a small area
• Placement of standard cells near the macros
• High pin density at the edges of macros due to high fan in cells like
AOI, OAI
• Bad floorplan (no proper blockages, halos are present)
• Macros/standard cell might have used all the metal layers inside and
routing resources will be less
• Placing macros at the center instead of the boundary.
• During IO optimization tool does buffering so lot of cells placed in the
core area
How to control the congestion:
• High cell density can cause the congestion.by default the cell
density can be up to 95%. We can reduce the cell density in
congested areas by using coordinate option.
• Set_congestion_options –max_util 0.45 –coordinate {x1 y1 x2
y2}
• Here we set the maximum cell density upto 45% and given the
coordinates for the particular area.
• If the design is congested, we rerun the place_opt with the –
congestion and –effort high options. During congestion driven
placement, the cells which are sitting together and caused the
congestion are spread apart.
• Place_opt –congestion_driven –effort high
• Reduce the local cell density using partial placement blockages
• Create_placement_blockage –boundary {10 20 100 200} –type
partial –blocked_percentage 40 (it means 40 % area is blocked
for placement of standard cells and the rest of the 60% available
for placement of standard cells)
• If we have more pin density, which can be reduced by adding cell
padding to the cells which is causing congestion. Cell padding can be
applied by setting the keepout margin command.
• Create_keepout_margin –type soft –outer {10 10 10 10}
my_lib_macro
• Macro padding or placement halos, soft blockages and hard
blockages  around the macros are like placement blockages around
the edges of the macros. This makes sure that no standard cells are
placed near the pins of macros and corners of macros, thereby
giving extra breathing space for the macro pin connections to
standard cells.
• change the floorplan (macros placement, macro spacing and pin
orientation)
• Reordering the scan chains to reduce the congestion
 Checks after placement:
• Check legalization
• Check PG connections for all the cells.
• Check congestion, density screens & pin density maps all these
should be under control
• Timing QOR, there should not be any high WNS violations.
• Minimum max Tran and max cap violations.
• Check whether all don’t touch cells & nets are preserved.
• Check the total utilization of design after placement.
THANK YOU