1.

Structure of MOS transistor

• MOSFET: metal oxide semiconductor field effect transistor
• Compared to BJT, MOSFET occupies smaller silicon area
and its fabrication involve fewer processing steps.
• MOS is a 4 terminal device (Body, drain, gate, source)
• It consist of P type substrate in which two diffusion
regions (source and drain) are formed.

Oxide layer
• Surface of substrate region between drain and source is covered with thin oxide
layer and metal or polysilicon. Gate is deposited on the top of this gate dielectric.
• The two region are current conducting terminals of this device.
• The device structure is completely symmetrical w.r.t. drain and source region.
Different roles of these two region will be defined only in conjunction with applied
terminal voltages and the direction of current flow.
• A conducting channel will be formed through applied gate voltage in the section
between drain and source region.
• Distance between drain and source is called channel length (L) and the lateral
extent of the channel (perpendicular to the length dimension) is the channel
width (W).
• A MOS transistor which has no conducting region at zero gate bias is called an
“enhancement type MOSFET”.
• If conducting channel is already exist at zero bias, the device is called “depletion
type MOSFET”.
• N channel MOSFET: MOSFET with P type substrate and with source and drain
region, the channel region to be formed on the surface is n type, such a device is
called n channel MOSFET.
• P channel MOSFET: MOSFET with N type substrate and with source and drain
region, the channel region to be formed on the surface is p type, such a device is
called P channel MOSFET.
• Abbreviation used are:
G : gate gate to source voltage
D : drain to source voltage
S : source to source voltage
B : body

• Source is defined as region which has lower potential than

the other region called drain.
• All terminal voltages are defined w.r.t. source potential.
• Charge carriers in MOS transistor are entered through
source, leave through drain and control through gate
voltage.
• Symbol : enhancement type MOSFET
• Symbol : depletion type MOSFET

PMOS :

NMOS:
 2. Operation of MOSFET
(a) Enhancement mode transistor action: NMOS
(i) With no gate voltage applied or with no bias condition
• When no bias voltage applied to gate, two back to back diode exist in
series between drain and source.
• One is formed by PN junction between drain region and P type
substrate, other is formed by PN junction between source region and P
type substrate.
• These back to back diode prevent conduction between drain and
source.

(ii) MOSFET under external device:

• Assume that = 0 and let the gate voltage be the controlling parameter.
• Depending on the magnitude of , three different operating region can
be observed for the MOS system: accumulation, depletion, inversion
Accumulation mode: if negative is applied to the gate, the
holes are attracted to the semiconductor – oxide interface.
Hence holes are accumulated at the surface that’s why
these is called carrier accumulation.
 depletion mode: Now small positive gate voltage is
applied. Holes in P type silicon are repelled due to positive
voltage. Hence depletion region is created near the surface.
No charge carrier present in the depletion region.
 inversion mode: Now further increase in gate voltage,
holes are repelled and electrons are attracted near the
surface. The n type region is created near the surface, is
called inversion layer and condition is called surface
inversion. These condition occurred when electron on the
surface = no. of holes in p type substrate
Part 1
• Principle of operation is to control the current conduction
between the source and drain, using the electric field
generated by the gate voltage as a control variable.
• For (positive voltage), the holes are repelled back into the
substrate and the surface of P type is depleted. Since
surface is devoid of any mobile carriers, current
conduction between drain and source is not possible.
• Now is further increased. The voltage needed to cause
surface inversion is called threshold voltage (). Channel is
created between drain and source and current conduction
will starts.
Part 2
• Now the influence of and different mode of drain current
will be examined for
• At thermal equilibrium exist and is equal to 0.
• If > 0 (small) is applied, drain current flow from source to
drain through channel. The operation is called linear mode
or linear region. In these condition channel region act as a
voltage controlled resistor.
• As increases, inversion layer change and channel depth
decrease at the drain end.
• At inversion charge at drain is reduced to zero which is
called pinch off point. These is done due to reverse bias at
drain side increases because number of electron increases
and due to reverse bias depletion region increases.
Channel will be decreases.
• Beyond A depleted surface region from adjacent to the
drain grows towards the source with the increasing drain
voltages. This mode is called saturation mode. In there
effective channel is reduced.
Characteristics of NMOS transistor in enhancement mode
 (b) Enhancement mode transistor action: PMOS
Part 1:
• When we supply negative voltage on gate, electron
present in N type silicon are repelled but current does not
start flowing from source to drain. This is occurs when <
• When we increase voltage beyond threshold voltage,
electrons are completely repelled and holes are starts
moving from source to drain and channel is created. Current
increases linearly.
Part 2 : for
• When is apply, due to negative voltage of holes are attracted and
current starts flowing linearly.
• Voltage is further increased and due to these negativity or reverse
bias increases and width of depletion region increases and channel
decreases and at saturation voltage , channel reduces to zero at
drain side. Current is saturated at that time.
• Beyond channel reduces from drain side towards source.
(c) Depletion mode transistor action: NMOS
Part 1:
• when is applied, minority carrier electrons are attracted towards
the channel due to and electrons are flow from source to drain due
to and current increases linearly.
• When is applied electrons are repelled and holes are attracted
towards channel and recombination occurs and number of electrons
decreases and also decreases.
Part 2:
• When small positive voltage of is applied, electrons moves
from source to drain and current increases linearly.
• Now is further increased, more number of electron are
attracted towards drain. Due to electron negativity, reverse
bias increases and depletion region width increases and
channel width decreases and reduces to zero at certain
voltage. After these current is saturated.
• When is increased beyond channel shrink towards source.
Characteristics of NMOS transistor
Characteristics of PMOS transistor
3. MOS Capacitor
 In MOSFET, capacitance exists between every two of the four
terminals. The value of these capacitances depends on the bias
condition of the transistor.
 From figure, we observe that capacitance exist between
(i) oxide capacitance between gate and channel (C1)
(ii) depletion capacitance between the channel and substrate (C2)
(iii) capacitance due to overlap of the gate polysilicon with the source and drain areas (C3
and (C4)
(iv) junction capacitance between the source/drain area and the substrateb(C5 and C6)
4. Current – Voltage characteristics of MOSFET
 The whole concept of MOS transistor evolves from the use of a
voltage on the gate to induce a charge in the channel between
source and drain, which may then be caused to move from S to D
under the influence of an electric field created by voltage applied
between drain and source.
 Since the charge induced is dependent on the gate to source voltage
, then is dependent on both . Consider a following figure in which
electrons will flow from source to drain:
 ………………………(i)

where
= electric field ( drain to source)

 =

 So

 ……………………………………. (ii)
4(i) The non – saturated region
 Charge induced in channel due to gate voltage is due to the voltage
difference between the gate and the channel
 The voltage along the channel varies linearly with distance X from
the source due to the IR drop in the channel and assuming that the
device is not saturated then the average value is
 The effective gate voltage is the threshold voltage needed to invert
the charge under the gate and establish the channel.
 Charge/unit area =
 Thus induced charge WL
where

= 4.0 for silicon dioxide

= permittivity of free space = 8.85 *

where D = oxide thickness

 Put the value from equation (ii) and (iii) In equation (i)

 =

 =

 = {}
 = K {}

 In the non – saturated or resistive region: < and K=

 Put β =
 = β {}

 Gate channel capacitance =

 So we can write K =

 So that = {}
4(ii) The saturated region
 Saturation begins when = - since at this point the IR drops in the
channel equals the effective gate to channel voltage at the drain and
we may assume that the current remains fairly constant as
increases further. Thus
 = K {}

 = K

 =

 =
5. MOSFET Scaling
 VLSI fabrication technology is still in the process of evolution which is
leading to smaller line widths and feature size and to higher packing
density of circuit on chip.
 The scaling down of feature size generally leads to improved
performance and it is important to understand the effect of scaling.
 Microelectronic technology may be characterized in terms of several
figure of merit: commonly used are:
(i) minimum feature size
(ii) number of gates on one chip
(iii) power dissipation
(iv) maximum operational frequency
(v) die size
(vi) production cost
 Many of these figure of merit can be improved by shrinking the
dimension of transistors, interconnection and the separation between
features, and by adjusting doping levels and supply voltages.
 The most commonly used models are the:
(i) constant electric field scaling
(ii) constant voltage scaling
 The following figure indicates the device dimension and substrate doping level which are
associated with the scaling of a transistor.
 Two scaling factors 1/α and 1/β are used.
 1/β is chosen as the scaling factor for supply voltage and gate oxide thickness D
 1/α is used for all other linear dimensions, both vertical and horizontal to the chip surface.
5.1 Scaling factors for device parameters
A. Gate area
Where L is channel length and W is channel width. Both are scaled by 1/α . Thus

B. Gate capacitance per unit area or

Where is the permittivity of the gate oxide and D is the gate oxide thickness which is
scaled by 1/β.
Thus is scaled by = β

C. Gate capacitance L W
Thus is scaled by β.
D. Parasitic Capacitances
Where d is the depletion width aroun source and drain which is scaled by 1/α and is the area of
the depletion region around source and drain which is scaled by .
Thus is scaled by . = 1/α

E. Carrier density in channel =

Where is the average charge per unit area in the channel in the “ON” state. is scaled by β and
is scaled by 1/β. Thus is scaled by 1.

F. Channel resistance =
Where µ is the carrier mobility in the channel and is assumed constant.
thus is scaled by . 1 = 1

G. Gate delay
Thus is scaled by 1. =
H. Maximum operating Frequency =
Where inversely proportional to delay .
Thus is scaled by

I. Saturation Current =
Where both are scaled by 1/β thus we have = 1/β

J. Current density J =
Where A is the cross sectional area of the channel in the ‘ON’ state which is scaled by . Thus J is
scaled by =

K. Switching energy per gate =

Where is scaled by =
L. Power dissipation per gate = +
Where is the static component = =
And dynamic component = =
Thus is scaled by

M. Power dissipation per unit area =

Where is scaled by =

N. Power speed product =

Where is scaled by =
6. Short channel devices
 A MOSFET is considered to be short when the channel length is the same order of
magnitude as the depletion layer width of the source and drain junction.
 As the channel length L is reduced to increase both the operation speed and the
number components per chip, the short channel effects arise.
 The short channel effects are attributed to two physical phenomena:
a) The limitation imposed on electron drift characteristics in the channel
b) The modification of the threshold voltage due to the shortening channel
length.
 Five different short channel effects can be distinguished:
a) drain induced barrier lowering and punchthrough
b) surface scattering
c) velocity saturation
d) impact ionization
e) hot electrons
6.1 Drain induced barrier lowering and punch through
 When the depletion regions surrounding the drain extends to the source, so that
the two depletion layer merge, punchthrough occurs.
 Punchthrough can be minimized with thinner oxides, larger substrate doping,
shallower junction and with longer channels.
 The current flow in the channel depends on creating and sustaining an inversion
layer on the surface.
 If the gate bias voltage is not sufficient to invert the surface, the carriers
(electrons) in the channel face a potential barrier that blocks the flow.
 Increasing gate voltage reduces the barrier potential and eventually allows the
flow of carrier under the influence of the channel electric field.
 In small geometry MOSFET, the potential barrier is controlled by both the
 If the drain voltage is increased, the potential barrier in the channel decreases,
leading to drain induced barrier lowering (DIBL).
 The reduction of the potential barrier eventually allows electron flow between the
source and the drain, even if the gate to source voltage is lower than the
threshold voltage. The channel current that flows under this condition ( is called
the sub-threshold current.
6.2 Surface scattering
 As the channel length becomes smaller due to the lateral extension of the
depletion layer into the channel region, the longitudinal electric field component
increases and the surface mobility becomes field dependent.
 Since the carrier transport in a MOSFET is confined within the narrow inversion
layer and the surface scattering (that is the collisions suffered by the electrons
that are accelerated toward the interface by causes reduction of the mobility, the
electron moves with great difficulty parallel to the interface, so that the average
surface mobility, even for small values of is about half as much as that of the bulk
mobility.
 Movement of electrons constitutes current ; The current depends upon electron
mobility and electric field ; Gate is isolated by oxide ; On the other side channel
forms a kind of capacitance along which an electric field exists ; Electric field is
positive [gate] to negative [Channel]
 The electrons are attracted by the positive Gate field ; They keep bouncing and
crashing against the oxide surface . This reduces the mobility of the carriers [ just
like you are crowded in a railway station / Bus stand where you cannot travel
faster due to random movement of passengers/visitors . That is Surface
scattering.
6.3 Velocity saturation
 The performance of short channel devices is also affected by the velocity
saturation.
 From the physics of semiconductor it is proved that the velocity of charge carrier
is linearly proportional to the electric field and the proportionality constant is
called as mobility of carrier.
 But when we increase the electric field beyond certain velocity called as thermal
velocity or saturated velocity, the velocity of the charge carrier does not change
with electric field.
 The electric field at which the velocity of carrier saturates is called as the critical
electric field.
 In MOSFET, when electric field along the channel reaches a critical value the
velocity of carriers tends to saturate and the mobility degrades.
 When we increase drain to source voltage, the electric field in the channel
reaches the critical value.
 Due to this the carriers at the drain are velocity saturated.
 At low electric field , the electron drift velocity in the channel varies linearly with
the electric field intensity.
6.4 Impact Ionization
 Another undesirable short channel effect, especially in NMOS, occurs due to the high
velocity of electrons in presence of high velocity of electrons in presence of high
longitudinal fields that can generate electron hole pairs by impact ionization, that is, by
impacting on silicon atoms and ionizing them.
 Impact ionization is the process in a material by which one energetic charge carrier can lose
energy by the creation of other charge carriers.
 As gate length is reduced, electric field at the drain in saturation increases, keeping fixed
drain voltages.
 It happens as follows normally, most of the electrons are attracted by the drain, while the
holes enter the substrate to form part of the parasitic substrate current.
 Moreover the region between the source and the drain can act like the base of an npn
transistor, with the source playing the role of the emitter and the drain that of the collector.
 If the mentioned holes are collected by the source and the corresponding hole current
creates a voltage drop in the substrate material of the order of 6V, the normally reverse
biased substrate source p-n junction will conduct appreciably.
 Then electrons can be injected from the source to the substrate, similar to the injection of
electrons from the emitter to the base. They can give enough energy as they travel toward
the drain to create new e-h pairs.
 The situation can worsen if some electrons generated due to high fields escape the drain
field to travel into the substrate, thereby affecting other devices on the chip.
6.5 Hot electrons
 Another problem related to high electric fields is caused by hot electrons.
 This energy electrons can enter the oxide, where they can be trapped, giving rise to oxide
charging that can accumulate with time and degrade the device performance by increasing
and affect adversely the gate’s control on the drain current.
7. MOS Inverters : Static Characteristics
 The inverter is the most fundamental logic gate that performs a Boolean operation on a
single input variable. In this topic, we will examine the DC (static) characteristics of various
MOS inverter circuits.
 The logic symbol and the truth table of the ideal inverter are shown in Fig 1. In MOS
inverter circuits, both the input variable A and the output variable B are represented by
node voltages, referenced to the ground potential.
 Using positive logic convention, the Boolean (or logic) value of "1" can be represented by a
high voltage of , and the Boolean (or logic) value of "0" can be represented by a low voltage
of 0.
 The DC voltage transfer characteristic (VTC) of the ideal inverter circuit is shown in Fig.2.
 The voltage is called the inverter threshold voltage.
 For any input voltage between 0 and = /2 , the output voltage is
equal to VDD (logic" 1 ).
 The output switches from to 0 when the input is equal to .
 For any input voltage between and , the output voltage assumes
a value of 0 (logic "0"). Thus, an input voltage 0 < Vin < is
interpreted by this ideal inverter as a logic "0," while an input
voltage < < is interpreted as a logic " 1."
 The DC characteristics of actual inverter circuits will obviously
differ in various degrees from the ideal characteristic shown in
Fig. 2.
 The accurate estimation and the manipulation of the shape of
VTC for various inverter types are actually important parts of the
design process.
7.1 NMOS Inverters : general structure
 Figure shows the generalized circuit structure of an NMOS inverter.
 The input voltage of the inverter circuit is also the
gate-to-source voltage of the NMOS transistor
( = ), while the output voltage of the circuit is equal
to the drain-to-source voltage ( = ). The source
and the substrate terminals of the NMOS transistor
also called the driver transistor are connected to ground
potential; hence the source-to-substrate voltage is = 0.
 In this generalized representation, the load device is
represented as two-terminal circuit element with
terminal current and terminal voltage .
 One terminal of the load device is connected to the drain
of the n-channel MOSFET, while the other terminal is
connected to , the power supply voltage.
 We will see that the characteristics of the inverter
circuit actually depend very strongly upon the
type and the characteristics of the load device.
Voltage transfer characteristics
 Applying Kirchhoff s Current Law (KCL) to this simple circuit,
we see that the load current is always equal to the NMOS
drain current.
 The voltage transfer characteristic describing as a function
of under DC conditions.
 The typical VTC of a realistic NMOS inverter is shown in Fig.
 From fig. we can observe that for very low input voltage
levels, the output voltage is equal to the high value of
(output high voltage).
 In this case the driver NMOS transistor is in cut-off and
hence does not conduct any current. Consequently the
voltage drop across the load device is very small in
magnitude and the output voltage level is high. As the
input voltage increases, the driver transistor starts
conducting a certain drain current and the output voltage
eventually starts to decrease.
 This drop in the output voltage level does not occur
abruptly such as the vertical drop assumed for the ideal
inverter VTC, but rather gradually and with a finite slope.
 We identify two critical voltage points on this curve where
the slope of the ( characteristic becomes equal to –1 i.e.
 The smaller input voltage value satisfying this condition is called the input low voltage and
the larger input voltage satisfying this condition is called the input high voltage .
 As the input voltage is further increased, the output voltage continues to drop and reaches
a value of (output low voltage). The inverter threshold voltage , which is considered as
the threshold voltage is defined as the point where on the VTC.
 Thus, a total of five critical voltages characterize the DC input-output voltage behavior of
the inverter circuit.
 functional definitions for the first four of these critical voltages are given below:
7.2 Resistive load Inverters
 In the figure of resistive load inverter circuit an
enhancement type NMOS transistor acts as the driver
device.
 The load consists of a simple linear resistor .
 The power supply voltage of this circuit is .
 The drain current of the driver MOSFET is equal to
the load current in the DC operation.
 = K

 =
7.3 Inverters with n-type MOSFET load
 In most digital VLSI system applications, resistive load inverter is not
used, because the load resistor occupies large area.
 The main advantage of using a MOSFET as the load device is that the
silicon area occupied by the transistor is usually smaller than that
occupied by a comparable resistive load.
 Moreover, inverter circuits with active loads can be designed to have
better overall performance compared to that of passive-load
inverters.
 The development of inverters with an enhancement-type MOSFET
load precedes other active-load inverter types, since its fabrication
process was perfected earlier.
7.3.1 Enhancement load NMOS inverter
7.3.2 Depletion load NMOS inverter
7.4 CMOS Inverters