Digital Fundamentals

Floyd

Chapter 8

© 2009 Pearson Education

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Half-Adder
Basic rules of binary addition are performed by a
Inputs Outputs
half adder, which has two binary inputs (A and
A B Cout S
B) and two binary outputs (Carry out and Sum). 0 0
0 0
0 1 0 1
The inputs and outputs can be summarized on a 1 0 0 1
truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

 
A 
A
Cout
B Cout B

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder
Inputs Outputs
A B Cin Cout S
By contrast, a full adder has three binary
0 0 0 0 0
inputs (A, B, and Carry in) and two binary 0 0 1 0 1
outputs (Carry out and Sum). The truth table 0 1 0 0 1
summarizes the operation. 0 1 1 1 0
1 0 0 0 1
A full-adder can be constructed from two 1 0 1 1 0
half adders as shown: 1 1 0 1 0
1 1 1 1 1
 
A A  A  Sum

B B Cout B Cout A 
B
Cout
Cin Cin

Cout Symbol

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder   0 Sum
1 A  1 A 

0 B Cout 0 B Cout 1

For the given inputs, determine 1

Cout
the intermediate and final outputs 1
of the full adder.
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Full-Adder

Notice that the result from the previous example can be

read directly on the truth table for a full adder.

Inputs Outputs
A B Cin Cout S
  0 Sum
0 0 0 0 0 1 A  1 A 
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 0 B Cout 0 B Cout 1
1 0 0 0 1
1 0 1 1 0 1 Cout
1 1 0 1 0
1 1 1 1 1 1

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A 4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout  Cout  Cout  Cout 

C4
C3 C2 C1
   

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).

1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimize the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Comparators
The function of a comparator is to compare the magnitudes of two
binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?

AND the outputs of four XNOR gates.

A1
B1
A2
B2 Output
A3
B3
A4
B4

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Comparators
IC comparators provide outputs to indicate which of the numbers is
larger or if they are equal. The bits are numbered starting at 0, rather
than 1 as in the case of adders. Cascading inputs are provided to
expand the comparator to larger numbers.

COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
The IC shown is the
B2
B3 3 4-bit 74LS85.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Comparators
IC comparators can be expanded using the cascading inputs as
shown. The lowest order comparator has a HIGH on the A = B input.
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders

Assume the output of the decoder shown is a

logic 1. What are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders
IC decoders have multiple outputs to decode any
combination of inputs. For example the binary-to-decimal
decoder shown here has 16 outputs – one for each
combination of binary inputs. Bin/Dec
0 1
1 1
2 1
3 1
4 1
1 A0 5 1
6 1
4-bit binary 1 A1 7 1 Decimal
input 0 A2 8 1 outputs
9 1
1 A3 10 1
11 0
12 1
13 1
14 1
15 1

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders
X/Y
0
A specific integrated circuit 1
decoder is the 74HC154 (shown as 2
3
a 4-to-16 decoder). It includes two 4

active LOW chip select lines which A0 1

5
6
must be at the active level to enable A1 2 7
A2
the outputs. These lines can be used A3
4
8
8
9
to expand the decoder to larger 10

inputs. 11
12
13
14
CS1 & 15
CS2 EN
74HC154

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders
The 74LS138 is a 3-to-8 decoder with three chip select inputs (two
active LOW, one active HIGH). In this Multisim circuit, the word
generator (XWG1) is set up as an up counter. The logic analyzer
(XLA1) compares the input and outputs of the decoder.

Inputs are blue, outputs are red.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders

How will the waveforms change if the word generator is

configured as a down counter instead of an up counter?

Inputs are blue, outputs are red.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders
The chip select inputs can be used to expand a decoder. In this circuit,
two 74LS138s are configured as a 16 line decoder. Notice how the MSB
is connected to one active LOW and one active HIGH chip select.

The next slide

shows the logic
analyzer output…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Decoders

Is the word generator set as an up counter or a down counter? (The least

significant decoder output at the top). It is an up counter.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD/DEC
Decoders 0
(1)
(2)
1
(3)
2
(15) (4)
BCD-to-decimal decoders accept a binary A0
(14)
1 3
(5)
coded decimal input and activate one of ten A1 2 4
A2 (13) 4 5
(6)
possible decimal digit indications. (12)
8 (7)
A3 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
decoder are the sequence 0101, 0110, 9
0011, and 0010. Describe the output.
74HC42

All lines are HIGH except for one active output, which
is LOW. The active outputs are 5, 6, 3, and 2 in that
order.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-
seven segment display with active LOW outputs.
VCC

(16)
BCD/7-seg
The a-g outputs are BI/RBO
(4)
BI/RBO
designed for much (7)
1
a
(13)
(12)
higher current than most BCD
(1)
2
b
c
(11)
Outputs
(2)
devices (hence the word inputs
(6)
4
d
(10) to seven
8 (9) segment
driver in the name). (3)
e
(15) device
LT LT f
(5) (14)
RBI RBI g

74LS47 (8)

GND

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 11 10
RBI c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decoder/Driver
The 74LS47 features leading zero suppression, which
blanks unnecessary leading zeros but keeps significant
zeros as illustrated here. The BI/RBO output is connected
to the RBI input of the next decoder.
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

Blanked Blanked Depending on the display type, current

limiting resistors may be required.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
BCD Decoder/Driver
Trailing zero suppression blanks unnecessary trailing
zeros to the right of the decimal point as illustrated here.
The RBI input is connected to the BI/RBO output of the
following decoder.
0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

1 0 0

Decimal Blanked Blanked

point

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Encoders
An encoder accepts an active logic level on one of its
inputs and converts it to a coded output, such as BCD or
binary.
1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the active
4
digit. The basic logic diagram is 5 A2
6
shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Encoders
The 74HC147 is an example of an IC encoder. It is has ten
active-LOW inputs and converts the active input to an
active-LOW BCD output. V CC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. This means that if more (1)
3
1 (9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
input 4 output
with the highest order decimal (3)
(4)
6
8
(14)
digit will be active. (5)
7
8
(10)
9
(8)
74HC147
The next slide shows an application … GND

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
VCC

Encoders R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3
1
4 2
5 4 BCD complement of
6
4 5 6 7
8 key press
8
9

R1 R2 R3 74HC147

1 2 3

R0
The zero line is not needed by the
0 encoder, but may be used by other
circuits to detect a key press.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Gray Code 1 bit 2 bits 3 bits

0 0 0 0 00
1 0 1 0 01
____

1 1 0 11
10 0 10
1 10
1 11

1 01
1 00

© 2009 Pearson Education

 Summary
Code converters

There are various code converters that change one code to

another. Two examples are the four bit binary-to-Gray
converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Multiplexers
A multiplexer (MUX) selects one data line from two or
more input lines and routes data from the selected line to
the output. The particular data line that is selected is
determined by the select inputs.
MUX
Two select lines are shown 0
S0 0
Data 1
here to choose any of the select S1
1
four data inputs.
D0 0 Data
D1 1 output
Data
D 2
inputs D2
Which data line is selected 3 3
if S1S0 = 10?D2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Demultiplexers
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
DEMUX
previously as a decoder but can also A0
Y0
Data
serve as a DEMUX. When select A1
Y1
Y2
connected as a DEMUX, data is lines A2 Data
Y3
applied to one of the enable inputs, Y4
outputs
and routed to the selected output Enable G1
Y5
G2A
line depending on the select inputs
G2B
Y6
variables. Note that the outputs are Y7

active-LOW as illustrated in the 74LS138

following example…

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary A0
A1
Demultiplexers
A2
Determine the outputs, given the
inputs shown. G1
G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
DEMUX Y1
Y0
Data A0 Y2
Y1
select A1
lines A2
Y2
Data
Y3
Y3
Y4
outputs Y4
Enable G1
G2A
Y5
Y5
inputs Y6
G2B Y6
Y7

74LS138 Y7
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Parity Generators/Checkers
Parity is an error detection method that
uses an extra bit appended to a group of
bits to force them to be either odd or
even. In even parity, the total number of
ones is even; in odd parity the total
number of ones is odd.

The ASCII letter S is 1010011. Show the parity

bit for the letter S with odd and even parity.

S with odd parity = 11010011

S with even parity = 01010011

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved