Sequential Logic

ENEL 111
Sequential Logic Circuits
 So far we have only considered circuits where 1
7

the output is purely a function of the inputs 3

 With sequential circuits the output is a

function of the values of past and present
inputs
A
X

X=X+A

This particular example is not very useful

 Sequential Circuits - Aims
 To be able to differentiate between the various types of bistable
circuits (and know when it is appropriate to use one type or
another)
 To describe the structure and operation of simple registers, shift
registers and binary counters
 To sketch and explain the features of a timing diagram for an n-bit
register
 To be able to connect an IC (integrated circuit) counter to create a
modulo-n counter or to cascade several counters to extend the
range
 To generate a state transition diagram from the description of a
problem, or to follow the flow of a given state transition diagram
 To apply the general sequential machine design method to
sequential circuits such as counters
Latches and Flip Flops
 Latches
 SR latch
 Clocked SR latch
 D Latch
 Flip flops
 Master-slave
 Edge triggered
 JK
Sequential circuit concepts
The addition of a memory device to a combinational circuit
allows the output to be fed back into the input:

Input(s) Output(s)
circuit

memory

Introduction to Digital Electronics, Crowe and Hayes Gill, Newnes, ISBN0-340-64570-9

Synchronous and Asynchronous
Input(s) Output(s)
circuit

memory

Clock pulse

 With
synchronous circuits a clock pulse is used to regulate the
feedback, input signal only enabled when clock pulse is high –
acts like a “gate” being opened.

Latches
The SR Latch
 Consider the following circuit

R Q R R Q Q

S S Q Q
S Q
Symbol
Circuit

R S Qn+1 n+1 represents output

0 0 Qn at some future time
0 1 1
1 0 0
1 1 ?
Function Table n represents current
output.
SR Latch operation
 Assume some previous operation has Q as a 1
 Assume R and S are initially inactive

Indicates a stable state at

R=0 some future time (n+ =
Q=1 R S Qn+1 now plus)
0 0 Qn
0 1 1 ~Q = Q, ie is the
S=0 Q=0 1 0 0 complement of Q.
1 1 ?
Circuit

Now assume R goes first to 1 then returns to 0, what happens:

Reset goes active
R=1
When R goes active 1, the output Q=0
from the first gate must be 0.

This 0 feeds
S=0 ~Q = 1
back to gate 2

Since both inputs are 0 the output is forced to 1

The output ~Q is fed back to

gate 1, both inputs being 1 R=1
the output Q stays at 0. Q=0

S=0 ~Q = 1
Reset goes in-active
R=0
Q=0
When R now goes in-active 0, the
feedback from ~Q (still 1), holds Q at 0.

S=0 ~Q = 1
The “pulse” in R has changed
the output as shown in the
function table:

R S Qn+1
We went from here 0 0 Qn
0 1 1 And back again
To here 1 0 0
1 1 ?
In that process, Q changed from 1 to 0. Further signals on R will
have no effect.
Set the latch
Similar sequences can be followed to show that setting S to 1 then 0 –
activating S – will set Q to a 1 stable state.
When R and S are activated simultaneously both outputs will go to a 0

R=1
Q=0

S=1 ~Q = 0

When R and S now go inactive 0, both inputs at both gates are 0

and both gates output a 1.
This 1 fedback to the inputs drives the outputs to 0, again both
inputs are 0 and so on and so on and so on and so on.
Metastable state
Ina perfect world of perfect electronic circuits the
oscillation continues indefinitely.

However, delays will not be consistent in both gates so the

circuit will collapse into one stable state or another.
R S Qn+1
This collapse is unpredictable. 0 0 Qn Future output = present output
0 1 1 Set the latch
Thus our function table: 1 0 0 Reset the latch
1 1 ? Don’t know
Latches
 The SR Latch
 NAND Form produces similar result from inverted inputs

R Q R S Qn+1
R R Q Q
0 0 ?
0 1 0
S Q S Q 1 0 1
S Q
1 1 Qn
Circuit Symbol Function Table

You ought to be able to figure this one out yourself!

Application of the SR Latch
 An important application of SR latches is for recording
short lived events
 e.g. pressing an alarm bell in a hospital
bed1
R Q light
RS
Latch
1 S
bed1
button bed2
R Q light
bed2 RS
button Latch
1 S warning
bell

1 master
reset
The Clocked SR Latch
 In some cases it is necessary to disable the inputs to a
latch
 This can be achieved by adding a control or clock input to
the latch
 When C = 0 R and S inputs cannot reach the latch
 Holds its stored value
 When C = 1 R and S inputs connected to the latch
 Functions as before

R
Q

Q
S
Clocked SR Latch

R S C Qn+1
R R Q Q X X 0 Qn Hold
C 0 0 1 Qn Hold
C
0 1 1 1 Set
S S Q Q 1 0 1 0 Reset
1 1 1 ? Unused
Clocked D Latch
 Simplest clocked latch of practical
importance is the Clocked D latch
D S
Q

Q
R

• It means that both active 1 inputs at R and S can’t occur.

• Notice we’ve reversed S and R so when D is 1 Q is 1.

D Latch
 It removes the undefined behaviour of the SR latch
 Often used as a basic memory element for the short term
storage of a binary digit applied to its input
 Symbols are often labeled data and enable/clock (D and C)

D
S Q Q
D Q D C Qn+1
C C X 0 Qn Hold
R Q Q C Q 0 1 0 Reset
1 1 1 Set

Circuit Symbol Function Table

Transparency
 The devices that we have looked so far are
transparent
 That is when C = 1 the output follows the input
 There will be a slight lag between them
1
C
0 When the clock
t “gate” opens,
1
changes in input
D
0 take effect at
t outputs –
1
Q transparency. Also
0 known as “level-
t
triggered”.
Propagation Delay, set-up and hold
(for transparent circuits)
Propagation delay:
Time taken for any change at inputs to affect outputs
(change on D to change on Q).

Setup time:
Data on inputs D must be held steady for at least this time
before the clock changes.

Hold time:
Data on inputs D must be held steady for at least this time
after the clock changes.
Clocked D Latch – Timing
Diagram

clock

clock enables input to be “seen”

output follows input in here
Latches - Summary
 Two cross-coupled NOR gates form an SR (set and
reset) latch
 A clocked SR latch has an additional input that controls
when setting and resetting can take place
 A D latch has a single data input
 the output is held when the clock input is a zero
 the input is copied to the output when the clock input is a one
 The output of the clocked latches is transparent
 The output of the clocked D latch can be represented by
the following behaviour D C Q n+1
X 0 Qn Hold
0 1 0 Reset
1 1 1 Set
Latches and Flip Flops
Terms are sometimes used confusingly:
A latch is not clocked whereas a flip-flop is
clocked.
A clocked latch can therefore equally be referred
to as a flip flop (SR flip flop, D flip flop).
However, as we shall see, all practical flip flops
are edge-triggered on the clock pulse.
Sometimes latches are included within flip flops as
a sub-type.
Flip-flops
 Propagation Delay
 Will the output of the following circuit ever be a 1?
A
Q

20

Q
B
A

 The brief pulse or glitch in the output is caused by the

propagation delay of the signals through the gates
Latches and Flip Flops

Clocked latches are level triggered. While the

clock is high, inputs and thus outputs can change.
This is not always desirable.

A Flip Flop is edge-triggered – either by the

leading or falling edge of the clock pulse.

Ideally, it responds to the inputs only at a

particular instant in time.

It is not transparent.
D-type Latch – Timing Review
D S
Q

1
C
0
The high part t
1
represents D
active 1, the low 0
t
part active 0. 1
Q
0
t
Positive edge-triggered D Flip-flop
Timing D Q

~Q

Q
initially
unknown
Master Slave D Flip-flop
 A negative edge triggered flip-flop
Master Slave
D Y D Q

C C Q

On the negative edge of the clock, the master

captures the D input and the slave outputs it.
The master-slave Flip-flop
Master Slave
D P
Q

P Q

No matter how long the clock pulse, both circuits cannot be active at the
same time.
D-type Positive Edge Triggered Flip-
flop
S
Q
CLK
Q’
R

 The most economical flip-flop - uses fewest

gates
JK Flip-flop Q
J

 The most versatile of the flip-flops

 Has two data inputs (J and K) K Q

 Do not have an undefined state like SR flip-flops

 When J & K both equal 1 the output toggles on the +ve edge triggered
active clock edge JK flip-flop

 Most JK flip-flops based on the edge-triggered

principle
J K C Qn+1
 The C column indicates 0 0  Qn Hold
+ve edge triggering 0 1  0 Reset
1 0  1 Set
(usually omitted)
1 1  Qn Toggle
X X X Qn Hold
Example JK circuit
J Q
A
C
E
Ck

F
B D
K ~Q

• Assume Q = 0, ~Q = 1, K = 1 J K C Qn+1
0 0  Qn Hold
• Gate B is disabled (Q = 0, F = 1)
0 1  0 Reset
• Make J = 1 to change circuit, when Ck = 1, all 1 0  1 Set
inputs to A = 1, E goes to 0, makes Q = 1 1 1  Qn Toggle
• Now Q and F are both 1 so ~Q = 0 and the circuit X X X Qn Hold
has toggled.
Timing diagram for JK Flip-flop
Negative Edge Triggered

clock

toggle hold reset set

J=K=1 J=K=0 J= 0 K=1 J= 1 K=0
Clock Pulse

The JK flip flop seems to solve all the problems

associated with both inputs at 1.
However the clock rise/fall is of finite duration.

If the clock pulse takes long enough, the circuit

can toggle.
For the JK flip flop it is assumed the pulse is quick

enough for the circuit to change only once.

ideal / actual edge pulse

JK from D Flip-flop

J
D Q

K
CLK C Q’
Summary
Flip flops are circuits controlled by a clock.

Triggered on the edge of the pulse to avoid races with

both inputs at 1 during the clock pulse.

Because modern ic’s have a small propagation delay

races can still occur.

The master-slave configuration solves this problem by

having only master or slave active at any one time.
What you should be able to do
Explain the difference between combinational and
sequential circuits
Explain the basic operation of SR and D latches.

Explain the operation of SR and JK flip flops.

Explain the operation of master-slave flip flops.

Draw simple timing diagrams for clocked latches and

edge-triggered flip flops.

Define setup and hold times for a transparent latch.