MOS Transistors – Basics

BY:-
Ajay Pratap Singh

VLSI Design 1
 MOS Transistor

NMOS PMOS

Enhancement Depletion Enhancement Depletion

Type Type Type Type

CMOS Bi-CMOS

VLSI Design 2
 NMOS
NMOS––Enhancement Type
Depletion Type

Source Drain Thick (Field) Oxide

Gate

n+ n+

p-substrate

Thin (Gate) Oxide

VLSI Design 3
 Gate Drain
Source

Thick (Field)
Oxide

n+ n+

L
p-substrate

Thin (Gate)
Oxide

Three Dimensional View of an NMOS

VLSI Design 4
 CMOS : N-Well Process

Source Drain Drain Source

Gate Gate

n+ n+ p+ p+

n-well
p-substrate

VLSI Design 5
 CMOS : P-Well Process

Source Drain Drain Source

Gate Gate

p+ p+ n+ n+

p-well
n-substrate

VLSI Design 6
 CMOS : Twin-Tub Process

Source Drain Drain Source

Gate Gate

p+ p+ n+ n+

n-well p-well

Lightly doped epitaxial layer

n+ or p+ substrate

VLSI Design 7
 MOS Transistors act as switches
 Switches are of two types –
 Normally Open
 Normally Closed
 Similarly MOS Transistors are of two types
 ENHANCEMENT type - which is analogous to OPEN
switch. i.e. NO CHANNEL between Source and Drain
 DEPLETION type - which is analogous to CLOSED switch.
i.e. CHANNEL ALREADY EXISTS between Source and
Drain
Gate
Source Drain

n+ n+

VLSI Design 8
 An effort is required to CLOSE an OPEN switch and to OPEN a
CLOSED switch
 Similarly to FORM the CHANNEL between the source and the drain
in ENHANCEMENT type, and to DEPLETE the CHANNEL
completely between the source and the drain in DEPLETION type
transistors, an energy is required

 This energy is supplied by the GATE Potential ( VGS) applied

between the GATE and the SOURCE and the minimum value of
such potential is known as THRESHOLD POTENTIAL (Vt)

VLSI Design 9
 VVGSGS<VVt t
Enhancement type transistor operates similar
to a normally open switch

+++++++ Typically Vt = 0.2 VDD

n+ n+

VGSV
VGS =0td
Depletion type transistor operates similar to
a normally closed switch

Typically Vtd = – 0.6 VDD

n+ n+

VLSI Design 10
 MOSFET Symbols

D D D D D D

G Sub G G G Sub G G

S S S S S S

NMOS NMOS
Enhancement Type Depletion Type

D D D D D D

G Sub G G G Sub G G

S S S S S S

PMOS PMOS
Enhancement Type Depletion Type

VLSI Design 11
Detailed Operation – NMOS Enhancement type
VGSV
= 0t

G
S D

++++++++++

n+ n+

L
L
p-substrate

VDS V
=DSV=>
> GS0
0– VtT
VLSI Design 12
Fluid Dynamic Analog of MOSFET Operation
MOSFET operation can be understood more clearly by considering
fluid dynamic analog for its operation
Here, we consider an NMOS enhancement type transistor
Source and Drain correspond to two large tanks filled with water

VGS

Source Tank Drain Tank

Electrons correspond to water molecules and the Electric current

corresponds to the flow of water
The two tanks are separated by a piston and a short thick handle is
attached to the piston
The depth at which the handle is with respect to Source level
corresponds to VGS

VLSI Design 13
 VGS < Vt

VGS

n+ n+
Source Tank
Drain Tank

When the level of piston is high providing no communication between

Source and Drain tanks, there is no water flow between them

Similarly, in a MOSFET, when VGS is less than the threshold voltage (Vt),
no channel is formed between Source and Drain and hence no current
flows

VLSI Design 14
 VGS  Vt

VGS +++++++
VGS n+ n+
Source Tank
Drain Tank
VDS = 0

As the piston moves downwards, and its level exceeds certain threshold
value, a channel is formed between Source and Drain tanks
Again, there is no water flow because water at source and drain are at the
same level
Similarly, in a MOSFET, when VGS is increased and when it exceeds the
threshold voltage (Vt), a channel is formed connecting Source and Drain
However, there is no current flow as potential at source and drain are
same (VDS=0)

VLSI Design 15
 VGS > VT

VDS +++++++
VGS
n+ n+

Source Tank Drain Tank VDS =0

DS > 0

When the water level at drain tank is lowered, then water from Source
which is at a higher level flows to Drain. The level of water in the drain
tank with respect to source tank corresponds to VDS

Similarly, in a MOSFET, when a higher potential is applied at the Drain

compared to Source (VDS > 0), current starts flowing from Drain to Source
(this corresponds to electrons flowing from source to drain)

VLSI Design 16
 VGS > VT

VDS +++++++
VDS
VGS
n+ n+

Source Tank Drain Tank V

VDS
DS=
DS
=00VGS – VT
>

As the difference in the water levels between source and drain tanks
(VDS) increases the water flow increases corresponding to a linear
increase in drain current
However, the cross sectional area of the connecting line (Channel)
reduces towards the drain end
This makes a decrease in the flow rate (rate of raise of drain current)
Hence after a critical value of drain voltage (VDS = VGS – Vt), the drain
current starts saturating
When the channel depth at the drain end becomes zero, the channel is
said to be pinched off and it is the point of start of drain current saturation.

VLSI Design 17
 VGS > Vt
Channel
Depletion
Region
+++++++

n+ n+

V DS=
VDS > 0V
VGS –V
GS – Vtt

(VGS – Vt) (VDS – (VGS – Vt))

When VDS > VGS – Vt, the current remains constant, but the channel
length decreases.
Now there are two regions for current flow which are in series. One is the
channel (low resistive) region and the other is the depletion (high
resistive) region between channel and the drain
Most of the drain voltage drops across this high resistive region giving
rise to constant current.
The current flowing in the channel is drift current and that from channel to
drain is diffusion current.

VLSI Design 18
The following things can be summarized for NMOS
enhancement transistor
 When VGS = 0, no channel is formed and the transistor is not
conducting
 For VGS  Vt, the channel is formed between Source and Drain

 Now when VDS > 0, the transistor starts conducting. It can be

proved that the current increases linearly with the drain source
voltage. This region is called linear or resistive region
 As VDS increases, the reverse bias at the drain end increases.
This makes the depletion width at the drain to increase. Since
the net charge should remain the same, the channel depth
decreases at the drain end
 When VDS = VGS – Vt, the channel depth at drain end becomes
zero

VLSI Design 19
 This is known as PINCH OFF and for further increase in drain
voltage, the channel length starts decreasing

 Now the region between source and drain is divided into two
regions – a low resistive channel region and a high resistive
depletion region between the channel and the drain

 The drain current has two components – a drift current due to

channel and a diffusion current from channel to drain

 Since here the high resistive depletion region dominates over

the low resistive channel region, the drain current gets
saturated. Thus the drain current is said to be saturated for
VDS  VGS – Vt

 For the same value of VDS, if VGS is increased, more carriers

are injected into the channel and hence the drain current is
increased

VLSI Design 20
IDS-VDS Characteristics of Enhancement Type NMOS Transistor

VDS = VGS – Vtn VGS5> VGS4

VGS4> VGS3

Saturation
IDS VGS3> VGS2

VGS2 > VGS1

Resistive

VGS1 = Vtn

0
VDS

VLSI Design 21
Biasing for other types of transistors and their operations

NMOS Depletion Type

Channel exists even when VGS = 0

We have to apply a negative potential

===V00td
VGSGS
VVGS
to the gate w.r.t. source to deplete the
channel. Thus the threshold potential
(Vtd) is negative for NMOS depletion
type transistors
n+ n+ When VGS = Vtd, the channel is
p-substrate completely depleted
The polarity of VDS is same as for
enhancement type NMOS and the
VDS characteristics are similar except that
the transistor conducts even with
VGS = 0

VLSI Design 22
PMOS Enhancement Type
No channel exists for VGS = 0

VV ==V0tp We have to apply a negative potential

GSGS
to the gate w.r.t. source to form the
channel. Thus threshold potential (Vtp)
is negative for PMOS enhancement
+++++++++
type transistors
p+ +++++++++++++++++ p+
When VGS = Vtp, holes are injected
n-substrate
underneath the gate and the channel
is formed between Source and Drain
The polarity of VDS is opposite as for
VDS
enhancement type NMOS and the
characteristics are similar but in 3rd
quadrant

VLSI Design 23
IDS-VDS Characteristics of Enhancement Type PMOS Transistor
VDS
0
VGS1 = Vtp
Saturation
Resistive
VGS2< VGS1

VGS3< VGS2 IDS

VGS4< VGS3

VGS5< VGS4 VDS = |VGS – Vtp|

VLSI Design 24
PMOS Depletion Type
Channel exists even when VGS = 0

VV
V ===V00tpd
GSGS
GS
We have to apply a positive potential
to the gate w.r.t. source to deplete the
channel. Thus threshold potential (Vtpd)
is positive for PMOS depletion type
+++++++++
transistors
p+ +++++++++++++++++ p+
When VGS = Vtpd, the channel is
n-substrate
completely depleted
The polarity of VDS is same as for
enhancement type PMOS and the
VDS
characteristics are similar except that
the transistor conducts even with
VGS = 0

VLSI Design 25