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Design of Computer

The document discusses the design of computer components including registers, data formats, instruction formats, memory reference instructions, branch instructions, register reference instructions, shift operations, input-output instructions, computer timings, control logic, and the execution of instructions in fetch and execute cycles.

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Aayush Fadia
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© © All Rights Reserved
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Download as PPTX, PDF, TXT or read online on Scribd
13 views

Design of Computer

The document discusses the design of computer components including registers, data formats, instruction formats, memory reference instructions, branch instructions, register reference instructions, shift operations, input-output instructions, computer timings, control logic, and the execution of instructions in fetch and execute cycles.

Uploaded by

Aayush Fadia
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DESIGN OF COMPUTER

Block diagram of Digital Computer

2
List of Registers for Computer

3
Data Formats

4
Instruction Format

5
Memory Reference Instructions

6
Demonstration of Branch to Subroutine
Instruction

7
Register Reference Instructions

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Shift Operations
Shift Right Operation
E

A16, A15,……….A1
Shift Left Operation
E

A16, A15,……….A1
9
Input-Output Instructions

10
Input Subroutine
100: SKI
BUN 100
INP
BUN 100

11
Computer Timings Signal

12
Block Diagram of Control Logic

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Execution of Instructions
• Logic design of computer
• Specify Micro operations for each machine
cycle with help of
– Timing signals to-t3
– Decoded operations q0-q7
– Status bits
• F=0 is fetch cycle
• F=1 is Execute cycle
14
Fetch Cycle

15
Fetch Cycle
• The opcode in I is decoded during t3
• Next step depends on value of qi, i = 0…7 that
produces 1 in the output of the decoder
• If decoded output is a memory-reference
instruction, an operand may be needed.
• If not, the instruction may be executed during t3.
• BUN instruction (opcode 5), register reference
instructions and input-output instructions do not
need a second access to memory
16
Fetch Cycle
• When opcode is 0,1,2,3,4 is encountered, the
computer has to go to execute cycle to access
the memory again
F’(q0+q1+q2+q3+q4)t3 : F  1
• The BUN instruction does not need operand
from memory
• q5t3 : PC  B(AD)

17
Register Transfer Operations during Fetch
Cycle

Register reference instructions are recognized as q6 and


input output instructions from q7

18
Execute Cycle
Common Operations for Execute Cycle
F is equal to 1 during this cycle
Instruction to be executed are specified by qi = 0 to 7.
AND 0 (q value)
ADD 1
STO 2
ISZ 3
BSB 4

19
Execution of Memory-reference Instructions

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Execution of Register-Reference Instructions

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