UNIT IV

PIC MICROCONTROLLER
 AGENDA
• Introduction to PIC
• Features
• Architecture
• Programming model(memory organization)
• Oscillator options
• BOD, power down modes
• Configuration bit settings
• Peripheral support
• Comparison of 10f,12f,16f and 18f PIC controller
families
• Overview of instruction set
 SYLLABUS
• Comparison of PIC family, Criteria for Choosing
Microcontroller, features, PIC18FXX architecture with
generalized block diagram.
• MCU, Program and Data memory organization, Bank
selection using Bank Select
• Register, Pin out diagram, Reset operations, Watch Dog
Timers, Configuration registers and oscillator options
(CONFIG).
• Power down modes , Brief summary of Peripheral support,
Overview of instruction set.
 Introduction to PIC
• In 1989, Microchip technology introduced an
8 bit controller called PIC
• PIC: Peripheral Interface Controller.
• The PIC family:
– 10xxx, 12xxx, 14xxx, 16xxx,17xxx and 18xxx
• PIC 18xxx is the highest performing
microcontroller from the PIC family
• It is available in 18-pin to 80-pin packages.
 Features of PIC 18fxx
• High speed RISC Architecture
• Operating frequency for PIC 18 DC to 40 MHz
• General features include: Timers, Watch dog
timers, ADC, Extended Instruction / Data
memory , Serial communication , Capture/
Compare/ Pulse width modulation (CCP).
• PIC 18 can have 2MB of program ROM memory. ROM may be of
different types such as (flash, OTP, UV-EPROM etc.)
– 21 bit PC available
– On chip ROM: Flash :F and OTP:C
• PIC can have maximum of 4KB of data RAM.
– The RAM consists of two components:
• GP RAM
• SFRs
• EEPROM 256 Bytes for storing critical data.(optional)
• It uses 16-bit wide instructions, 8-bit wide data path.
• 5 I/O ports available for PIC18f4520
– PORT A through PORT E
– Each port can be configured as input or output.-Bidirectional port
– Each port has some other functions Such as timer , ADC, interrupts
and serial communication
 Features: PIC 18F452
• Power Management Features
• Flexible Oscillator Structure
• Wide Operating Voltage Range: 2.0V to 5.5V
• High-Current Sink/Source 25 mA/25 mA
• Many on chip peripherals available.
– Up to three Programmable External Interrupts
– Counter/Timer modules.
• Modules 0,2 (8-Bits)
• Modules 1,3 (16-Bits)
– Up to two CCP Modules/ ECCP module
• The CCP module is a peripheral which allows the user to time and
control different events
– ADC 10-bits with 8-way input multiplexer.
 PIC 18F452 : Peripherals

– Master Synchronous Serial Port (MSSP) module

supporting 3-Wire SPI (all 4 modes) and I2C
Master and Slave modes
– Enhanced Addressable USART module
– Dual Analog Comparators with Input Multiplexing
– Programmable 16-Level High/Low-Voltage
Detection (HLVD) module:
• Supports interrupt on High/Low-Voltage Detection
Architecture of PIC 18f452
 WREG(Working Register)
• Only one 8 bit WREG in the PIC.
• Similar to accumulator of other controller
• WREG is used for all arithmetic and logic
instructions.
• Ex: MOVLW k ; move literal value k into WREG
MOVLW 25h ; move 25h into WREG
• ADDLW K ; add literal value k to WREG
ADD LW 35h ; add value 35h to W(W=W+35h)
• Moving a value larger than 255(FFh), into the
WREG will truncate the upper byte and cause a
warning in .err file.
 The file register
• The data memory space in PIC is a read/write
memory.
• The data memory is also called file registers.
• the file registers are used by the CPU for data
storage, scratch pad and registers for internal use.
• The file register data RAM in PIC is divided into two
sections:
– Special Function Registers(SFRs)
– General Purpose RAM(GP-RAM)
File Register and access bank in PIC18
• The PIC 18f can have maximum of 4KB (4096
bytes) of on chip RAM.
• With 4096 bytes ,the file register has an
addresses of 000-FFFh.
• The file register is divided into 256 byte
memory banks.
• Therefore maximum 16 (0-F) banks .
• At least one bank for file register is there in
every PIC. This bank is known as access bank.
• BSR: Bank Select Register (0 to F)
– 4-bit Register
– Provides upper 4-bits of 12-bit address of data memory
– Direct addressing
• FSR: File Select Registers
– FSR0, FSR1, and FSR2
– FSR: composed of two 8-bit registers
– FSRH and FSRL
– Used as pointers for data registers (indirect addressing)
– Holds 12-bit address of data register
• Instruction Decoder
– 16-bit Instructions
• STATUS: Flag Register
– 5 individual bits called flags
• Product
– 16-bit Product of 8-bit by 8-bit Multiply
• Program Counter (PC)
– 21-bit register functions as a pointer to program memory during
program execution
• Table Pointer
– 21-bit register used as a memory pointer to copy bytes between
program memory and data registers
• Stack Pointer (SP)
– 5-bit register used to point to the stack
• Stack
– 31 registers used for temporary storage of memory addresses during
execution of a program
 Program ROM organization
• PIC18F4520 each have 32 KB of Flash memory and can
store up to 16,384 single-word instructions.
• PIC18 devices have two interrupt vectors.
• The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
• The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
• A read from program memory is executed on one byte at a
time.
• A write to program memory is executed on blocks of 32
bytes at a time.
• Program memory is erased in blocks of 64 bytes at a time.
 Program Counter(PC)
• The PC is of 21 bits. Divided into three separate
8-bit registers.
– PCL <7:0>
– PCH <15:8>
– PCU <20:16>
• Lower byte accessible as readable and writable in
data memory.
• Upper bytes indirectly accessible via
PCLATH/PCLATU
• To prevent the PC from becoming misaligned with
word instructions, the Least Significant bit of PCL
is fixed to a value of ‘0’.
• The PC increments by 2 to address sequential
instructions in the program memory.
• 22nd bit used to access configuration memory
 Status Register

• C (Carry/Borrow Flag):
▫ set when an addition generates a carry and a subtraction generates a borrow
• DC (Digit Carry Flag):
▫ also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic
operation
• Z (Zero Flag):
▫ set when result of an operation is zero
• OV (Overflow Flag):
▫ set when result of an operation of signed numbers goes beyond seven bits
• N (Negative Flag):
▫ set when bit B7 is one of the result of an arithmetic /logic operation
 Stack
• The stack operates as a 31-word by 21-bit RAM .
• It is not part of either program or data space.
• 5-bit Pointer, STKPTR.
• The Stack Pointer is readable and writable.
– The address on the top of the stack is readable and writable through
the Top-of-Stack (TOS) Special Function Registers.
– Data can also be pushed to, or popped from the stack, using these
registers.
• A CALL type instruction causes a push onto the stack.
– The Stack Pointer is first incremented and the location pointed to by
the Stack Pointer is written with the contents of the PC (already
pointing to the instruction following the CALL).
• A RETURN type instruction causes a pop from the stack.
– The contents of the location pointed to by the STKPTR are transferred
to the PC and then the Stack Pointer is decremented
• For stack access, four registers are provided in the
Special Function Register (SFR) bank. They are:
– TOSU
– TOSH
– TOSL
– STKPTR
• The Stack Pointer is initialized to ‘00000’ after all Resets.
• There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this is
only a Reset value.
• Status bits indicate if the stack is full, or has overflown
or underflown.
• Only the top of the
return address stack
(TOS) is readable and
writable.
• A set of three registers,
TOSU:TOSH:TOSL, hold
the contents of the
stack location pointed
to by the STKPTR
register.
 Stack Pointer (STKPTR)

D7 D6 D5 D4 D3 D2 D1 D0

STKFUL STKUNF X SP4 SP3 SP2 SP1 SP0

D7: STKFUL: Stack full flag:

Set when stack is full or an overflow occurs
D6: STKUNF: Stack underflow flag:
Set when the stack underflow occurred.
D5: Unused
D4 to D0 bits: Stack Pointer
 CONFIGURATION REGISTERS
• The Configuration bits can be programmed
(read as‘0’) or left unprogrammed (read as ‘1’)
to select various device configurations.
• The configuration memory space (300000h-
3FFFFFh), can only be accessed using table
reads and table writes.
• The Configuration registers are written a byte
at a time.
 CONFIG 4L 85h
D7 D6 D5 D4 D3 D2 D1 D0

/DEBUG XINST X X X LVP X STVREN

• /DEBUG: Background Debugger Enable bit

– 1 = Background debugger disabled
– 0 = Background debugger enabled
• XINST: Extended Instruction Set Enable bit
– 1 = Instruction set extension and Indexed Addressing mode enabled
– 0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
• LVP: Single-Supply ICSP Enable bit
– 1 = Single-Supply ICSP enabled
– 0 = Single-Supply ICSP disabled
• STVREN: Stack Full/Underflow Reset Enable bit
– 1 = Stack full/underflow will cause Reset
– 0 = Stack full/underflow will not cause Reset
ON-CHIP RESET CIRCUIT
 RESET
• PIC18F have various reset signal as follows:
• MCLR
• WATCHDOG TIMER RESET
• BOR
• RESET INSTRUCTION
• STACK FULL RESET
• STACK UNDERFLOW RESET
 Reset facility available

• Power-on Reset (POR)

• MCLR Reset during normal operation
• MCLR Reset during power-managed modes
• Watchdog Timer (WDT) Reset (during execution)
• Programmable Brown-out Reset (BOR)
• RESET Instruction
• Stack Full Reset
• Stack Underflow Reset
 RCON: Reset Control

D7 D6 D5 D4 D3 D2 D1 D0

IPEN SBOREN X /RI /TO /PD /POR /BOR

• IPEN: Interrupt Priority Enable bit

• SBOREN: BOR Software Enable bit
• /RI: RESET Instruction Flag bit
• /TO: Watchdog Time-out Flag bit
• /PD: Power-Down Detection Flag bit
• /POR: Power-on Reset Status bit
• /BOR: Brown-out Reset Status bit
 Brown out Reset(BOR)
• BOR circuit that provides the user with a number
of configuration and power-saving options.
• The BOR is controlled by the BORV<1:0> and
BOREN<1:0> Configuration bits.
• BOR threshold is set by the BORV1:BORV0 bits.
• IF BOR is enabled, any drop of “VDD” below V BOR
will reset the device.
Chip will remain in Brown Out Reset until Vdd rises
about Vbor
CONFIG 2L 1Fh
D7 D6 D5 D4 D3 D2 D1 D0

X X X BORV1 BORV0 BOREN1 BOREN0 /PWRTEN

• BORV<1:0>: Brown-out Reset Voltage bits

– 11 =VBOR= 2.11V
– 10= VBOR = 2.79V
– 01= VBOR= 4.33V
– 00= VBOR=4.59V
• BOREN<1:0>: Brown-out Reset Enable bits
• /PWRTEN: Power-up Timer Enable bit
• *TPWRT= 65.5ms
• *TBOR=200usec

* Refer data sheet for values.

 BOR CONFIGURATION

BOR Configuration Status of

SBOREN BOR Operation
(RCON<6>)
BOREN1 BOREN0

0 0 Unavailable BOR disabled; must be enabled by

reprogramming the Configuration bits.
0 1 Available BOR enabled in software; operation controlled by
SBOREN.
1 0 Unavailable BOR enabled in hardware in Run and Idle modes,
disabled during Sleep mode.
1 1 Unavailable BOR enabled in hardware; must be disabled by
reprogramming the Configuration bits.
 Power on Reset
• This Pulse is generated on-chip whenever Vdd
rises above a certain threshold.

• This allows the device to start in the initialized

state when Vdd is adequate for operations.
• Svdd = 0.05V/ms: Rate at which Vdd must rise.
 Oscillator Configurations
• PIC18F4520 devices can be operated in ten different oscillator
modes. The user can program the Configuration bits,
FOSC<3:0>, in CONFIG1H to select one of these ten modes:
– LP Low-Power Crystal
– XT Crystal/Resonator
– HS High-Speed Crystal/Resonator
– HSPLL High-Speed Crystal/Resonator with PLL Enabled
– RC External Resistor/Capacitor with FOSC/4 Output on RA6
– RCIO External Resistor/Capacitor with I/O on RA6
– INTIO1 Internal Oscillator with FOSC/4 Output on RA6 and I/O on
RA7
– INTIO2 Internal Oscillator with I/O on RA6 and RA7
– EC External Clock with FOSC/4 Output
– ECIO External Clock with I/O on RA6
EXTERNAL OSCILLATOR OPTIONS
 INTERNAL OSCILLATOR
• The PIC18F4520 devices include an internal
oscillator block.
• This may eliminate the need for external oscillator
circuits on the OSC1 and/or OSC2 pins.
• two different clock signals INTOSC AND INTRC
• The main output (INTOSC) is an 8 MHz clock
source which can be used to directly drive the
device clock.
• The internal RC oscillator (INTRC),provides a
nominal 31 kHz output.
 OSCCON
D7 D6 D5 D4 D3 D2 D1 D0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFC SCS1 SCS0

• IDLEN: Idle Enable bit

– 1 = Device enters an Idle mode on SLEEP instruction
– 0 = Device enters Sleep mode on SLEEP instruction
• IRCF<2:0>: Internal Oscillator Frequency Select bits
– 111 = 8 MHz (INTOSC drives clock directly)
– 110 = 4 MHz
– 101 = 2 MHz
– 100 = 1 MHz
– 011 = 500 kHz
– 010 = 250 kHz
– 001 = 125 kHz
– 000 = 31 kHz (from either INTOSC/256 or INTRC directly)
• OSTS: Oscillator Start-up Timer Time-out Status bit
– 1 = Oscillator Start-up Timer (OST) time-out has expired;
primary oscillator is running
– 0 = Oscillator Start-up Timer (OST) time-out is running;
primary oscillator is not ready
• IOFS: INTOSC Frequency Stable bit
– 1 = INTOSC frequency is stable
– 0 = INTOSC frequency is not stable
• SCS<1:0>: System Clock Select bits
– 1x = Internal oscillator block
– 01 = Secondary (Timer1) oscillator
– 00 = Primary oscillator
 CONFIG 1H 07H
D7 D6 D5 D4 D3 D2 D1 D0

IESO FCMEN - - FOSC3 FOSC2 FOSC1 FOSC0

• IESO: Internal/External Oscillator Switchover bit

– 1 = Oscillator Switchover mode enabled
– 0 = Oscillator Switchover mode disabled
• FCMEN: Fail-Safe Clock Monitor Enable bit
– 1 = Fail-Safe Clock Monitor enabled
– 0 = Fail-Safe Clock Monitor disabled
• FOSC<3:0>: Oscillator Selection bits
ex:
– 0010 = HS oscillator
– 0001 = XT oscillator
– 0000 = LP oscillator
CLOCK DIAGRAM
 PIC18F Programming Model
• The representation of
the internal architecture
of a microprocessor,
necessary to write
assembly language
programs

• Divided into two groups

– ALU Arithmetic Logic
Unit (ALU)
– Special Function
Registers (SFRs) from
data memory
 Registers
• WREG
– 8-bit Working Register (equivalent
to an accumulator)
• BSR: Bank Select Register
– 4-bit Register (0 to F)
• Only low-order four bits are used to
provide MSB four bits of a12-bit
address of data memory.
• STATUS: Flag Register
 Flags in Status Register

• C (Carry/Borrow Flag):
– set when an addition generates a carry and a subtraction generates a borrow
• DC (Digit Carry Flag):
– also called Half Carry flag; set when carry generated from Bit3 to Bit4 in an arithmetic
operation
• Z (Zero Flag):
– set when result of an operation is zero
• OV (Overflow Flag):
– set when result of an operation of signed numbers goes beyond seven bits
• N (Negative Flag):
– set when bit B7 is one of the result of an arithmetic /logic operation
 File Select Registers (FSR)
• There are three registers:
• FSR0, FSR1, and FSR2
• Each register composed of two 8-bit
registers (FSRH and FSRL)
• Used as pointers for data
registers
• Holds 12-bit address of data
register
 Instruction set of PIC 18f4520
• The CPU can access data in various ways. The data
could be in any register, memory location, or provided
as an immediate value. These various ways of
accessing data are called addressing modes.
• The addressing modes supported by a up/uc, are
determined when it is designed and cannot be altered
by the programmer.
• The addressing modes supported by PIC18f are:
– Immediate
– Direct
– Register Indirect
– Indexed-ROM
 Addressing modes in brief
• Immediate:
– The operand is literal constant.
– Operand comes immediately after the opcode
when an instruction is specified.
– This addressing mode is used to load information
into WREG and selected registers but not in any
file registers.
ex: MOVLW 45H
ADDLW D’62’
• Direct:
• The entire data RAM file register can be
accessed using either direct or register indirect
addressing mode.
• In direct addressing mode, the operand data is
in a RAM memory location whose address is
known and this address is given as part of the
instruction.
ex: MOVWF 0X40
MOVFF 0X40,0X50
• Register indirect:
• In this addressing mode, a register is used as a pointer to the data
RAM location.
• In PIC18f, three registers are used for this purpose:
– FSR0, FSR1,FSR2 (FSR: File select register)
• The FSR is 12-bit register allowing access to entire 4096 bytes of
data RAM.
• Use instruction LFSR (load FSR) to load the RAM location .
ex: LFSR 0,0X30 MOVWF INDF0
LFSR 1,0X20
LFSR 2,0X40
• The FSRs are split into 8 bit registers. As FSRxL and FSRxH(only
lower 4 bits used).
• INDF(Indirect register) is associated with each FSR.
– INDF0,INDF1,INDF2
• The data pointed by FSRx is moved into INDFx register.
• Indexed ROM
• This addressing mode is widely used to access
data from the program ROM space of PIC18f
• It is also known as table processing.
• There are a group of instructions for table
processing(both read as well as write).
• TBLPTR(Table pointer) is an 21 bit SFR used to
point byte to be fetched from code memory.
– TBLPTR is divided into three 8-bit parts viz. TBLPTRL,
TBLPTRH, TBLPTRU.
• The other SFR register used for table processing
is TABLAT.
– The TABLAT is used to keep the byte once it is fetched
into the CPU.
 The instruction set is also grouped as:
• Byte oriented

• 15Bit OPCODE
oriented9 d 8 a 7 f(FileReg) 0

15 OPCODE 9 b 8 a 7 f(FileReg) 0
• Literal
15 OPCODE 8 7 k (Literal) 0

• Control
15 OPCODE 8 7 n (Literal) 0

15 1111 12 11 n <19:8> (Literal) 0

 The Bank Select Register again....

• movwf 0x070, 1 also written as: movwf 0x070, BANKED

• The execution of the above instruction depends on the value in the

Bank Select Register.

• If BSR = 0, then location 0x070 is modified.

• If BSR = 1, then location 0x170 is modified.
• If BSR = 2, then location 0x270 is modified....etc.

• movwf 0x070, 0also written as: movwf 0x070, a(ACCESS)

• The execution of the above instruction does NOT depend on the

value in the Bank Select Register, only the 8 bits in the machine
code is used for the address location.
• Location 0x070 is always modified.
 Rules for the ‘access’ bit in instructions
We will use the following rules for the value of the ‘a’ (Access) bit
in machine code produced for instructions that contain a data
memory address (these assumptions used by the MPLAB®
assembler)
a. If the data memory address is between 0x000 –0x07F or
between 0xF80 –0xFFF, assume the ‘a’ bit is a ‘0’ (ignore the
BSR).
b. If the data memory address is between 0x080 –0xF7F,
assume the ‘a’ bit is a ‘1’ (use the BSR).

We will NEVER write: movf 0x070, BANK

Always either “movf 0x070” (assume ACCESS, a = 0)
or “movf 0x170” (assume BANKED, a = 1).
 Changing the Bank Select Register
movwf f [,a] B
15
B
14
B
13
B
12
B
11
B
10
B B
9 8
B B B B
7 6 5 4
B B B B
3 2 1 0

0 1 1 0 1 1 1 a f f f f f f f f
fileReg (w)

mnemonic Machine code

movwf 0x070 0110 1110 0111 0000 = 0x6e70 (a=0)
movwf 0x170 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0x270 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0xF90 0110 1111 1001 0000 = 0x6e90 (a=0)

We will not specify the ‘a’ bit on instruction mnemonics.

 Machine code example for movwf
movwf 0x170 The instruction mnemonics are
For this to work, BSR must be 0x1! different, but the machine code
is the same! That is because
movwf 0x270 machine code only uses lower
For this to work, BSR must be 0x2!
8-bits of the address!!!

mnemonic Machine code

movwf 0x070 0110 1110 0111 0000 = 0x6e70 (a=0)
movwf 0x170 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0x270 0110 1111 0111 0000 = 0x6f70 (a=1)
movwf 0xF90 0110 1110 1001 0000 = 0x6e90 (a=0)

By default (after processor reset), BSR = 0x0 !!!!.

Comparison
• 2
• 70
• 0X270