Logic and Computer Design Fundamentals

Chapter 3 – Combinational
Logic Design
Part 2 – Encoder, Multiplexer, Adder

Charles Kime & Thomas Kaminski

© 2004 Pearson Education, Inc.
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Overview
 Part1 - Introduction
 Design Topics
• Design hierarchy
 Design Procedure
• The major design steps: specification, formulation,
optimization, technology mapping, and verification
 Technology Mapping
• From AND, OR, and NOT to other gate types
• Decoders
 Part 2
• Encoders
• Multiplexers
• Binary Adders

Chapter 3 - Part 1 2
 Encoding
 Encoding - the opposite of decoding - the conversion
of an m-bit input code to a n-bit output code with n £
m £ 2n such that each valid code word produces a
unique output code
 Circuits that perform encoding are called encoders
 An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding
to the input values
 Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corres-
ponding to the position in which the 1 appears.
Chapter 4 3
Encoder

Chapter 3 - Part 1 4
Encoder Example
 A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit Di is a 1, then the
output (A3, A2, A1, A0) is the BCD code for i,
 The truth table could be formed, but
alternatively, the equations for each of the
four outputs can be obtained directly.

Chapter 4 5
Decimal-to-BCD encoder

Chapter 3 - Part 1 6
 Encoder Example (continued)
 Input Di is a term in
equation Aj if bit Aj is 1 in
the binary value for i.
 Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
 F1 = D6 + D7 can be
extracted from A2 and A1 Is
there any cost saving?
Chapter 4 7
Encoder Example (continued)
A 3 = D8 + D9
A 2 = D4 + D5 + D6 + D7
A 1 = D2 + D3 + D6 + D7
A 0 = D1 + D3 + D5 + D7 + D9

Chapter 3 - Part 1 8
Priority Encoder
 If more than one input value is 1, then the
encoder just designed does not work.
 One encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
 Among the 1s that appear, it selects the most
significant input position (or the least
significant input position) containing a 1 and
responds with the corresponding binary code
for that position.

Chapter 4 9
Priority Encoder Example
 Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to
most significant 1 present - Code outputs A2, A1, A0 and V where V
indicates at least one 1 present.
No. of Min- Inputs Outputs
terms/Row D4 D3 D2 D1 D0 A2 A1 A0 V

1 0 0 0 0 0 X X X 0
1 0 0 0 0 1 0 0 0 1
2 0 0 0 1 X 0 0 1 1
4 0 0 1 X X 0 1 0 1
8 0 1 X X X 0 1 1 1
16 1 X X X X 1 0 0 1
 Xs in input part of table represent 0 or 1; thus table entries correspond
to product terms instead of minterms. The column on the left shows that
all 32 minterms are present in the product terms in the table

Chapter 4 10
Priority Encoder Example (continued)

 Could use a K-map to get equations, but

can be read directly from table and
manually optimized if careful:
A2 = D4
A1 = D4 D3 + D4 D3D2 = D4F1, F1 = (D3 + D2)
A0 = D4 D3 + D4 D3 D2D1 = D4(D3 + D2D1)
V = D4 + F1 + D1 + D0

Chapter 4 11
Selecting
 Selecting of data or information is a critical
function in digital systems and computers
 Circuits that perform selecting have:
• A set of information inputs from which the selection
is made
• A single output
• A set of control lines for making the selection
 Logic circuits that perform selecting are called
multiplexers
 Selecting can also be done by three-state logic
or transmission gates
Chapter 4 12
Multiplexers
 A multiplexer selects information from
an input line and directs the information
to an output line
 A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
 A multiplexer can be designed to have m
information inputs with m < 2n as well as
n selection inputs
Chapter 4 13
4-to-1-line Multiplexer

Chapter 3 - Part 1 14
2-to-1-Line Multiplexer
 Since 2 = 21, n = 1 S Y
 Selection variable S: 0 I0

• S = 0 selects input I0 1 I1

• S = 1 selects input I1
 The equation:
Y = SI0 + SI1
Enabling
 The circuit: Decoder Circuits

I0
Y
S
I1

Chapter 4 15
2-to-1-Line Multiplexer (continued)
 Note the regions of the multiplexer circuit
shown:
• 1-to-2-line Decoder
• 2 Enabling circuits
• 2-input OR gate
 To obtain a basis for multiplexer expansion, we
combine the Enabling circuits and OR gate into
a 2 ´ 2 AND-OR circuit:
• 1-to-2-line decoder
• 2 ´ 2 AND-OR

Chapter 4 16
Example: 4-to-1-line Multiplexer
 2-to-22-line decoder
 22 ´ 2 AND-OR
 Y = (S1 S0) I0 + (S1 S0) I1 + (S1 S0) I2 + (S1 S0) I3
Decoder
S1

4 3 2 AND-OR
S0
Decoder
S1

S0

I1
Y

I2

I3

Chapter 4 17
Combinational Function Implementation
 Alternative implementation techniques:
• Decoders and OR gates
• Multiplexers (and inverter)

Chapter 4 18
Combinational Function Implementation

 F(x,y,z) = Σ(1,2,6,7) using 4-to-1 multiplexer.

 Connect the variables x and y to the selection inputs S1, and S0.
The inputs of the multiplexers can be obtained from the truth
table as shown below.

Chapter 3 - Part 1 19
F(A, B, C, D) = Σ(2, 3, 5, 7, 10, 11, 15)

Chapter 3 - Part 1 20
Functional Blocks: Addition
 Binary addition used frequently
 Addition Development:
• Half-Adder (HA), a 2-input bit-wise addition
functional block,
• Full-Adder (FA), a 3-input bit-wise addition
functional block,
• Ripple Carry Adder, an iterative array to
perform binary addition, and
• Carry-Look-Ahead Adder (CLA), a
hierarchical structure to improve
performance.

Chapter 5 21
Functional Block: Half-Adder
 A 2-input, 1-bit width binary adder that performs the
following computations:
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
 A half adder adds two bits to produce a two-bit sum
 The sum is expressed as a X Y C S
sum bit , S and a carry bit, C
0 0 0 0
 The half adder can be specified
0 1 0 1
as a truth table for S and C 
1 0 0 1
1 1 1 0

Chapter 5 22
Logic Simplification: Half-Adder

 The K-Map for S, C is: S Y C Y

 This is a pretty trivial map!
By inspection: 0 11 0 1

X 12 3 X 2 13
S = X×Y+ X×Y = XÅ Y
 And C = X × Y

 The most common half

adder implementation is: X
Y S

S = XÅY C
C = X×Y

Chapter 5 23
 Functional Block: Full-Adder
 A full adder is similar to a half adder, but includes a
carry-in bit from lower stages. Like the half-adder, it
computes a sum bit, S and a carry bit, C.
• For a carry-in (Z) of Z 0 0 0 0
0, it is the same as X 0 0 1 1
the half-adder: +Y +0 +1 +0 +1
CS 00 01 01 10
• For a carry- in
(Z) of 1: Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
Chapter 5 24
Logic Optimization: Full-Adder
 Full-Adder Truth Table: X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
 Full-Adder K-Map: 1 1 0 1 0
1 1 1 1 1

S Y C Y

0
11 3
12 0 1
13 2

X 14 17 X 15 17 16
5 6 4

Z Z

Chapter 5 25
Equations: Full-Adder
 From the K-Map, we get:
S = XYZ+ XY Z+ XYZ+ XYZ
C = XY+XZ+YZ
 The S function is the three-bit XOR function (Odd
Function):
S = XÅYÅZ
 The Carry bit C is 1 if both X and Y are 1 (the sum is
2), or if the sum is 1 and a carry-in (Z) occurs. Thus C
can be re-written as:
C = X Y + (X Å Y) Z
 The term X·Y is carry generate.
 The term XY is carry propagate.

Chapter 5 26
Full-Adder Implement

S = A Å B Å Cin
Cout = AB + ( A Å B ) Cin

Chapter 3 - Part 1 27
4-bit Ripple-Carry Binary Adder
 A four-bit Ripple Carry Adder made from four
1-bit Full Adders:

B3 A3 B2 A2 B1 A1 B0 A

C3 C2 C1
FA FA FA C0

C4 S3 S2 S1 S0

Chapter 5 28
Carry Propagation & Delay
 One problem with the addition of binary numbers is
the length of time to propagate the ripple carry from
the least significant bit to the most significant bit.
 The gate-level propagation path for a 4-bit ripple carry
adder of the last example:
A3 A2 A1 A0
B3 B2 B1 B0

C3 C2 C1 C0

C4
S3 S2 S1 S0
 Note: The "long path" is from A0 or B0 though the
circuit to S3.
Chapter 5 29
Carry Lookahead
 Given Stage i from a Full Adder, we know that
there will be a carry generated when Ai = Bi =
"1", whether or not there is a carry-in. A B
i i
 Alternately, there will be Gi
a carry propagated if the
“half-sum” is "1" and a
carry-in, Ci occurs.
Pi
 These two signal conditions Ci
are called generate, denoted
as Gi, and propagate, denoted
as Pi respectively and are
Ci+1
identified in the circuit: Si
Chapter 5 30
Chapter 3 - Part 1 31
Carry Lookahead (continued)
 In the ripple carry adder:
• Gi, Pi, and Si are local to each cell of the adder
• Ci is also local each cell
 In the carry lookahead adder, in order to
reduce the length of the carry chain, Ci is
changed to a more global function spanning
multiple cells
 Defining the equations for the Full Adder in
term of the Pi and Gi:

Chapter 5 32
Carry Lookahead (continued)

Pi = Ai Å Bi Gi = Ai Bi
Si = Pi ÅCi Ci+1 = Gi + Pi Ci

Chapter 3 - Part 1 33
4-bit Carry Look-ahead Adder

Chapter 3 - Part 1 34
4-bit Carry Look-ahead Adder

Chapter 3 - Part 1 35
Carry Lookahead Development
 Ci+1 can be removed from the cells and used to derive a
set of carry equations spanning multiple cells.
 Beginning at the cell 0 with carry in C0:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1(G0 + P0 C0)
= G1 + P1G0 + P1P0 C0
C3 = G2 + P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0)
= G2 + P2G1 + P2P1G0 + P2P1P0 C0
C4 = G3 + P3 C3
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0
C0

Chapter 5 36