INTRODUCTION

TO THE
MICROPROCESSORS_3

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 Internal Architecture of MP
 8086/8088 M.Ps Internal Architecture
 There are two main functional logic blocks in the
8086/88 processors:
 1_ EU ‘Execution Unit’ - Its function is to execute
program instructions
 2_ BIU ‘Bus Interface Unit’ - Its function is to provide
interface between MP and memory and I/O units

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 Internal Architecture of MP

EU tells the BIU where to fetch the instruction

and data from,
Decodes the instruction and finally
Executes the instructions

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 Internal Architecture of MP

BIU controls the address, data, and control

busses and handles instruction fetch and
data read/write operations
The BIU and EU can operate in parallel
One task of the BIU is instruction “pre-fetch”,
that is, BIU fetches the next instructions and
places it in the ‘Instruction Queue’.

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Internal Units & Sub Units of MP

MP

BIU EU

Instruction Queue Arithmetic & Logic Unit

Segment Registers General Purpose Registers

Pointer Register Pointer & Index Registers

Summer Flag or Status Register

 Bus Interface Unit (BIU)

 Sub units of Bus Interface Unit (BIU):

i) Instruction Queue
ii) Segment Registers
iii) Pointer Register
iv) Summer

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 Bus Interface Unit (BIU)

Sub units of Bus Interface Unit (BIU):

‘Instruction Queue’ is a group of registers.
(It is now replaced by Cache memory).
The 8086 MP can have up to 6 bytes of
information in its instruction queue while
8088 MP can have up to 4 bytes of
information in its instruction queue.

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 Bus Interface Unit BIU(continued)
 Sub units of Bus Interface Unit (BIU):
 Segment Registers
 i) CSR (Code Segment Register)
 ii) DSR (Data Segment Register)
 iii) ESR (Extra Segment Register)
 iv) SSR (Stack Segment Register)
 The function of every Segment Register is to hold
the ‘Starting Address’ of its respective ‘Segment’,
which is present in the memory

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 Bus Interface Unit-BIU(continued)

Sub units of Bus Interface Unit (BIU):

Instruction Pointer(IP): It contains the offset address of
the next instruction to be fetched from the code
segment.
Summer : BIU computes the ‘Physical Address’ by
adding the contents of Code Segment Register (that is,
the ‘Starting Address’ of the Code segment) along with
the contents of IP by using ‘Summer’. The ‘sum’
physically appears as address on the Address Bus

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 Execution Unit (EU)

 Sub units of Execution Unit (EU):

i) Arithmetic & Logic Unit (ALU)
ii) General Purpose Registers
iii) Pointer & Index Registers
iv) Flag or Status Register

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 Execution Unit - EU (Continued)
 Sub units of Execution Unit (EU):
 ALU : Arithmetic & logic Unit
 This is the most important unit of a Microprocessor
 It performs all Arithmetic operations like Addition,
Subtraction, Multiplication, Division, Increment &
Decrement etc and also
 Performs Logic operations like AND, OR, NOT etc

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 Internal Architecture of MP
 Sub units of Execution Unit (EU):
 General Purpose Registers
 i) AX ( AH + AL)
 ii) BX (BH + BL)
 iii) CX (CH + CL)
 iv) DX (DH + DL)
 AX, BX, CX & DX are 16 bit registers, but can also be divided
into two parts, like AX = AH + AL, where
AH = Higher Byte of AX and AL = Lower Byte of AX
The general function of all of these register is to hold data, for
12 this they are similar BUT they have some special functions
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 Execution Unit - EU (Continued)
 General-Purpose Registers (cont)
 AX : ‘Accumulator register’ : Used for multiply, divide operations
and also used to hold data in I/O operations.
Means data to be multiplied or divided is kept in AX register, and
while performing I/O operation data is kept in it
 BX: Base Index: Used to hold the offset address of Data
segment.
 CX: Count: Used for count operations.
It holds the count for some instructions like ‘REP’ and ‘LOOP’ etc.
 DX: Data: Used to hold a portion of the result for multiply and
divide operations. Also used to hold the address of an I/O Device

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 Execution Unit - EU (Continued)

 Pointer & Index Registers

 SP : Stack Pointer Register
 BP : Base Pointer Register
 SI : Source Index Register
 DI : Destination Index Register
 All of these registers hold the ‘Offset
Address’ of their respective segments

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 Execution Unit - EU (Continued)
 Default Setting of Segment & Pointer Registers
 CSR : IP (for Code Segment)
 DSR : SI, DI, BX, a 16 Bit number (for Data segment)
 SSR : SP, BP (for Stack Segment)
 ESR : DI for String instructions (for Extra Segment)

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 Execution Unit - EU (Continued)
 BIU computes the ‘Physical Address’ by adding the
contents of Segment Register (that is, the ‘Starting
Address’ of the segment) along with the contents of
Pointer & Index Registers.
 This addition is done among the Segment & Pointer
registers as per the default setting (mentioned
earlier)
 The ‘Sum’ physically appears as ‘address’ on the
Address Bus and it is called as ‘Physical Address’

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 Execution Unit - EU (Continued)
 Flag or Status Register
 16 bit register but only 9 bits are active;
 6 bits are ‘Status bits’ & 3 bits are ‘Control bits’
 Status Bits: ZF, CF, AF, SF, OF, PF
 Control Bits: IF, DF & TF

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 Execution Unit - EU (Continued)
 Flag or Status Register (continued)
 All these bits are Flip Flops, which can be ‘Set’ or ‘Reset’
 Status Bits show the ‘Status’ or ‘Result’ of some operation,
like Arithmetic or Logic operation done by MP on some data,
by getting ‘Set’ or ‘Reset’
 For example if in an arithmetic operation, like subtraction, we
get a zero result then ZF: Zero Flag gets Set but if result is
not zero then ZF remains Reset, similarly if the result is
negative then SF: Sign Flag gets Set otherwise it the result
is positive SF remains Reset.

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 Execution Unit - EU (Continued)
 Flag or Status Register (continued)
 Control Bits are used to control some specific operations, by
making them ‘Set’ or ‘Reset’
 IF: Interrupt Flag is set to activate the ‘Interrupt’ input of the
MP, otherwise the interrupt input remains inactive
 DF: Direction Flag is used to set the direction
(i.e upward /downward or increment/decrement mode)
of SI & DI registers. It is used only with the String Cmnds.
 TF: Trap Flag is used to set mode of program execution of
the processor, so if TF is reset MP executes programs in
normal mode but if TF is Set the MP runs program in ‘Trap’
19 or ‘Debug’ mode.
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Sub Units

Segment Registers (In BIU)

i) CSR (Code Segment Register)
ii) DSR (Data Segment Register)
iii) ESR (Extra Segment Register)
iv) SSR (Stack Segment Register)
Sub Units

Pointer & Index Registers

i) I.P : Instruction Pointer
ii) SP : Stack Pointer Register
iii) BP : Base Pointer Register
iv) SI : Source Index Register
v) DI : Destination Index Register

 All of these registers hold the ‘Offset Address’ of their

respective segments
 Only I.P is in BIU whereas other are in EU
 Sub Units

General Purpose Registers(In EU)

i) AX ( AH + AL)
ii) BX (BH + BL)
iii) CX (CH + CL)
iv) DX (DH + DL)
AX, BX, CX & DX are 16 bit registers, but can also
be divided into two parts, like AX = AH + AL
Block Diagram of 8086/8088
Internal Architecture