ĐẠI HỌC BÁCH KHOA TP.

HCM
KHOA ĐIỆN – ĐIỆN TỬ

COMPUTER ENGINEERING I
(ECE290)
Digital System Design
with Verilog

Bộ môn Điện tử
16/05/2009
Combinational Circuit

2
Outline

• Conditional operator
• If-else statement
• Case statement
• Casex, casez
• Examples

3
Combinational circuits

inputs
0
1
outputs

w0 y0
w1 y1
y2
En y3

1) Outputs only depend on inputs

2) Could include: gates, multiplexers, encoders, decoders,
code converters, comparators …
3) Verilog description: gates, logic expression, behavior
4
Conditional operator
• Format
– Conditional_expression ? true_expression :
false_expression
• Behavior
– If the conditional expression is 1 (true), then the value of
true_expression is chosen;
– Otherwise, the value of false_expression is chosen
• Example
– A = (B<C) ? (D+5) : (D+2);
• Can be used in continuous assign and
procedural statements

5
2-to-1 multiplexer

s s f
w0 w0
f ( s, w0 , w1 )  s w0  sw1
0 0
f
w1 1 1 w1

w0 w0

s f s

w1 w1 f

6
 4-to-1 multiplexer

s0
s1 s1 s0 f
w0 00 0 0 w0
w1 01
s1
f 0 1 w1
w2 10 w2
w3 11
1 0 s0
1 1 w3

s0 w0 0
w0 w1 1
s1
0
w1 f
1
f
w2 0
w2
w3 1

w3
7
 Multiplexer examples

module mux2to1 (w0, w1, s, f); Conditional operator

input w0, w1, s; in continuous assignment
output f;

assign f = s ? w1 : w0; Conditional operator

in procedural statement
endmodule 
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;
reg f;

1) f is reg always @(w0 or w1 or s)

2) Include all input signals f = s ? w1 : w0;

endmodule  8
Nesting conditional operators

module mux4to1 (w0, w1, w2, w3, S, f);

input w0, w1, w2, w3;
input [1:0] S;
output f;
 
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);

endmodule 

9
if-else

• Format
if (conditional_expression) statement;
else statement; begin…end

• Behavior
– If the conditional_expression is true, then the
first statement is executed;
– Or else the second statement is executed.
• Used inside an always block, the
statements are procedural.
10
if-else examples

module mux2to1 (w0, w1, s, f);

input w0, w1, s;
reg data type
output f;
reg f;
Include all input signals
always @(w0 or w1 or s)
if (s= =0)
f = w0;
else
f = w1;

endmodule
11
 If… else if…else if

module mux4to1 (w0, w1, w2, w3, S, f); module mux4to1 (W, S, f);
input w0, w1, w2, w3; input [3:0] W;
input [1:0] S; input [1:0] S;
output f; output f;
reg f; reg f;

always @(w0 or w1 or w2 or w3 or S) always @(W or S)

if (S = = 2'b00) if (S = = 0)
f = w0; f = W[0];
else if (S = = 2'b01) else if (S = = 1)
f = w1; f = W[1];
else if (S = = 2'b10) else if (S = = 2)
f = w2; f = W[2];
else if (S = = 2'b11) else if (S = = 3)
f = w3; f = W[3];
12
endmodule endmodule
 s0
s1

w0

w3

w4 s2
s3
w7

w8

w11

w12

w15
A 16-to-1 multiplexer. 13
Hierarchical 16-to-1 Multiplexer

module mux16to1 (W, S16, f);

input [0:15] W;
input [3:0] S16;
output f;
wire [0:3] M;
 
mux4to1 Mux1 (W[0:3], S16[1:0], M[0]);
mux4to1 Mux2 (W[4:7], S16[1:0], M[1]);
mux4to1 Mux3 (W[8:11], S16[1:0], M[2]);
mux4to1 Mux4 (W[12:15], S16[1:0], M[3]);
mux4to1 Mux5 (M[0:3], S16[3:2], f);

endmodule  14
Case statement

• Format
1) Many possible alternatives
case(expression) 2) Expression and each alternative are
alternative1: statement; compared bit by bit.
alternative2: statement; 3) If there is a match, the statement is
executed
… 4) If the alternatives do not cover all
alternativej: statement; possibilities, default should be included.
[default: statement;] Otherwise, a sequential circuit will be
generated
endcase

15
 Multiplexer using case

module mux4to1 (W, S, f); s0

input [0:3] W; s1 s1 s0 f

input [1:0] S; w0 00 0 0 w0
w1 01 w1
0 1
output f; w2 10
f
1 0 w2
w3
reg f; 11
1 1 w3

always @(W or S)
case (S)
0: f = W[0];
1: f = W[1];
or binary numbers 2: f = W[2];
3: f = W[3];
endcase

endmodule
16
2-to-4 decoder

En w1 w0 y 0 y1 y 2 y 3
w0 y0
1 0 0 1 0 0 0
w1 y1
1 0 1 0 1 0 0
y2
1 1 0 0 0 1 0
En y3
1 1 1 0 0 0 1
0 x x 0 0 0 0
(a) Truth table (b) Graphical symbol

17
Decoder using case

module dec2to4 (W, Y, En);

input [1:0] W; Concatenate operator
input En; Default for En=0
output [0:3] Y;
reg [0:3] Y;

always @(W or En)

case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase

endmodule 18
Decoder using if-else, case

module dec2to4 (W, Y, En);

input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;

always @(W or En)

begin
if (En == 0)
Y = 4'b0000;
else
case (W)
0: Y = 4'b1000;
1: Y = 4'b0100;
2: Y = 4'b0010;
3: Y = 4'b0001;
endcase
end

endmodule
19
Hierarchical code for 4-16 decoder

module dec4to16 (W, Y, En);

input [3:0] W;
input En;
output [0:15] Y;
wire [0:3] M;

dec2to4 Dec1 (W[3:2], M[0:3], En);

dec2to4 Dec2 (W[1:0], Y[0:3], M[0]);
dec2to4 Dec3 (W[1:0], Y[4:7], M[1]);
dec2to4 Dec4 (W[1:0], Y[8:11], M[2]);
dec2to4 Dec5 (W[1:0], Y[12:15], M[3]);
 
endmodule

20
BCD-to-7-segment code

w3 w2 w1 w0 a b c d e f g

0 0 0 0 1 1 1 1 1 1 0
a a 0 0 0 1 0 1 1 0 0 0 0
w0 b 0 0 1 0 1 1 0 1 1 0 1
c f b
w1 0 0 1 1 1 1 1 1 0 0 1
w2 d g 0 1 0 0 0 1 1 0 0 1 1
e e c 0 1 0 1 1 0 1 1 0 1 1
w3
f
0 1 1 0 1 0 1 1 1 1 1
g d
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
(a) Code converter (b) 7-segment display 1 0 0 1 1 1 1 1 0 1 1

(c) Truth table

Two types of 7-segment display anode cathode

1)common-cathode: 1on; 0off
2)common-anode: 0on; 1off
21
BCD-to-7-segment decoder

module seg7 (bcd, leds);

input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds; comment

always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
6: leds = 7'b1011111;
7: leds = 7'b1110000; X  don’t-care
8: leds = 7'b1111111;
9: leds = 7'b1111011;
default: leds = 7'bx;
endcase
endmodule  22
ALU — 74381
// 74381 ALU
module alu(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;

always @(s or A or B)
case (s)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase

endmodule 
23
casex and casez

• case : bit-by-bit comparison {0,1,z,x}

case (s)
s1: … // 001  001; 0x10x1; zx0zx0
• casez: treat all z as don’t care
// 001  001; 0x10x1; 1x0zx0

• casex: treat all z and x as don’t care

// 001  001; 1001xx; 010z1x

24
Priority encoder
module priority (W, Y, z);
input [3:0] W;
output [1:0] Y;
output z;
reg [1:0] Y;
reg z;

always @(W)
begin
z = 1;
casex(W)
4'b1xxx: Y = 3;
4'b01xx: Y = 2;
4'b001x: Y = 1;
4'b0001: Y = 0;
default: begin
z = 0;
Y = 2'bx;
end
endcase
end
25
endmodule
Sequential circuit blocks
(1/2)

26
Outline

• Verilog for latch

• Edge-sensitive always block
• Verilog for flip-flops
• Non-blocking assignments
• Verilog for asyn and syn reset
• Verilog for registers

27
 Verilog for Latch

Clk D Qt + 1 module D_latch (D, Clk, Q);

0 x Qt  input D, Clk;
1 0 0
1 1 1 output Q;
reg Q;

D Q always @(D or Clk)

Clk Q
if (Clk)
Q = D;

endmodule
No else clause
Sensitivity list should include D and Clk

28
always block (overview)

• Level-sensitive always block

– always @ (signal1 or signal2)
– Used for combinational circuits and Latches
• Edge-sensitive always block
– always @ (posedge clk)
– Response to positive edge of clk signal
– always @ (negedge clk)
– Response to negative edge of clk signal
– Used for sequential circuits and flip-flops
29
 D flip-flop

D Q module flipflop (D, Clock, Q);

input D, Clock;
Clock Q
output Q;
reg Q;

always @(posedge Clock)

Sensitivity list contains only Clock Q = D;
Why?
endmodule

30
Assignments (overview)
• Continuous assignments – fixed connection
– assign f1 = a && b;
– assign f2 = ~ f1;
• Blocking assignments – evaluate in order
– = in always block
• begin
Q1 = D; // new Q1 will be used in evaluating all subsequent statements in this
block
Q2 = Q1; // new Q1 goes to Q2, so Q2 is equal to D.
• end
• No-blocking assignments – evaluate in parallel
– <= in always block
• begin
Q1<= D;
Q2<= Q1; // old Q1 goes to Q2
• end
– The order of statements doesn’t matter

31
Blocking and non-blocking assignments

Initially, Q1=10, Q2=0 Initially, Q1=10, Q2=0

always @ ( posedge clk) always @ ( posedge clk)

begin begin
Q1 = Q2 ; Q1 <= Q2;
Q2 = Q1 ; Q2 <= Q1;
end end
After one clk positive edge After one clk positive edge

What happens
if we change the
Q1=0, Q2=0 Q1=0, Q2=10 order of two statements?
Q1=Q2 Q1,Q2 exchange

32
Blocking assign

module example7_3 (D, Clock, Q1, Q2);

input D, Clock;
output Q1, Q2;
D D Q Q1
reg Q1, Q2;
Clock Q
always @(posedge Clock)
begin
Q1 = D; D Q Q2
Q2 = Q1;
end Q

endmodule
33
Two cascaded flip-flops

Non-blocking assignments

module example7_4 (D, Clock, Q1, Q2);

input D, Clock;
output Q1, Q2;
reg Q1, Q2;

always @(posedge Clock) D D Q

Q1
D Q
Q2

begin
Q1 <= D; Clock Q Q

Q2 <= Q1;
end

endmodule 34
 Example 7.5 (blocking)

module example7_5 (x1, x2, x3, Clock, f, g);

input x1, x2, x3, Clock;
output f, g;
reg f, g;

always @(posedge Clock) How about reversing the statements f and g?

begin x3
f = x1 & x2;
g = f | x3; x1 D Q g
x2
end Q

endmodule
D Q f

Clock Q

35
Example 7.6 (non-blocking)
module example7_6 (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output f, g;
reg f, g;

always @(posedge Clock)

begin
f <= x1 & x2; x3
g
D Q
g <= f | x3;
end Q

endmodule
x1
D Q f
x2

Clock Q

36
Recommendations

• It is better to use blocking assignments

when describing combinational circuits
• It is better to using non-blocking
assignments to describe sequential
circuits

37
T flip-flop

T Qt + 1
0 Qt 
module tff(t, clk,q);
1 Qt 
input t, clk;
(b) Truth table
output q;
reg q;

always @ (posedge clk)

Q
case(t)
T
0: q <= q;
Q 1: q <= ~q;
endcase
(c) Graphical symbol
endmodule

38
Quiz: write code for J-K ff

J K Q  t + 1
0 0 Q t J Q
0 1 0
1 0 1
K Q
1 1 Q t 

(b) Truth table (c) Graphical symbol

39
 Flip-flop with clear capability

module flipflop (D, Clock, Resetn, Q);

input D, Clock, Resetn;
output Q;
reg Q;

always @(negedge Resetn or posedge Clock)

if (!Resetn)
Q <= 0;
else
Q <= D;

endmodule

Asynchronous reset: by using sensitivity list and if-else

40
Flip-flop with clear capability

module flipflop (D, Clock, Resetn, Q);

input D, Clock, Resetn;
output Q;
reg Q;

always @(posedge Clock)

if (!Resetn)
Clear
Q <= 0; D Q Q
D
else
Q <= D; Clock Q Q

endmodule 

Synchronous reset: by using if-else

41
N-bit register

module regn (D, Clock, Resetn, Q);

parameter n = 16; D[n-1] Q[n-1]
input [n-1:0] D; D Q
input Clock, Resetn;
output [n-1:0] Q;
reg [n-1:0] Q;
  D Q
always @(negedge Resetn or posedge Clock)
if (!Resetn)
Q <= 0;
else
Q <= D; D[0]
D Q Q[0]
endmodule

Clock 42
 4-bit shift register
module muxdff (D0, D1, Sel, Clock, Q); module shift4 (R, L, w, Clock, Q);
input D0, D1, Sel, Clock; input [3:0] R;
output Q; input L, w, Clock;
reg Q; output [3:0] Q;
  wire [3:0] Q;
always @(posedge Clock)  
if (!Sel) muxdff Stage3 (w, R[3], L, Clock, Q[3]);
Q <= D0; muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);
else muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);
Q <= D1; muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);
 
endmodule endmodule

D
clock
sel
0 1
Circuit ?

D0 D1
43
Sequential circuit blocks
(2/2)

44
Outline

• Shift register
• Counter
• Bus structure

45
 4-bit shift register

module muxdff (D0, D1, Sel, Clock, Q); module shift4 (R, L, w, Clock, Q);
input D0, D1, Sel, Clock; input [3:0] R;
output Q; input L, w, Clock;
reg Q; output [3:0] Q;
  wire [3:0] Q;
always @(posedge Clock)  
if (!Sel) muxdff Stage3 (w, R[3], L, Clock, Q[3]);
Q <= D0; muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);
else muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);
Q <= D1; muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);
 
endmodule endmodule

D
sel clock
0 1
46
D0 D1
 4-bit shift register

module shift4 (R, L, w, Clock, Q); 4

R Q[3]
input [3:0] R;
input L, w, Clock; w
output [3:0] Q; Clock Q[0]
reg [3:0] Q;
always @(posedge Clock)
L
if (L)
Q <= R;
else Comments:
begin 1) This is a behavioral description
Q[0] <= Q[1]; 2) Only Clock is included in always list
3) Control signal L is used in if statement
Q[1] <= Q[2];
Q[2] <= Q[3];
Q[3] <= w;
end
endmodule 
47
 N-bit shift register

module shift4 (R, L, w, Clock, Q); module shiftn (R, L, w, Clock, Q);
parameter n = 16;
input [3:0] R;
input [n-1:0] R;
input L, w, Clock; input L, w, Clock;
output [3:0] Q; output [n-1:0] Q;
reg [3:0] Q; reg [n-1:0] Q;
always @(posedge Clock) integer k;
if (L)
Q <= R; always @(posedge Clock)
else if (L)
begin Q <= R;
else
Q[0] <= Q[1];
begin
Q[1] <= Q[2]; for (k = 0; k < n-1; k = k+1)
Q[2] <= Q[3]; Q[k] <= Q[k+1];
Q[3] <= w; Q[n-1] <= w;
end end
endmodule  endmodule 48
 Up-counter

module upcount (Resetn, Clock, E, Q);

input Resetn, Clock, E;
output [3:0] Q;
reg [3:0] Q;

always @(negedge Resetn or posedge Clock)

if (!Resetn)
Q <= 0;
else if (E)
Q <= Q + 1;

endmodule
Comments: asynchronous reset (why?); counting if enable (E) is high. 49
Up-counter with parallel load

module upcount (R, Resetn, Clock, E, L, Q);

input [3:0] R;
input Resetn, Clock, E, L;
output [3:0] Q;
reg [3:0] Q;

always @(negedge Resetn or posedge Clock)

if (!Resetn)
Q <= 0;
else if (L)
Q <= R;
else if (E)
Q <= Q + 1;
endmodule 50
Up-counter simulation

51
Frequency Divider by N

module clock_div(SlowClock, Reset, Clock);

input Reset, Clock;
output SlowClock;

reg SlowClock;
reg [19:0] ClockDiv;

parameter Maxcount = 4;
always @ (posedge Clock or negedge Reset)
if(!Reset)
begin
ClockDiv <= 0;
SlowClock <= 0;
end
else if (ClockDiv == Maxcount)
begin
SlowClock <= 1;
ClockDiv <=0;
end
else
begin
SlowClock <= 0;
ClockDiv <= ClockDiv+1;
end
endmodule
52
Simulation result

53
Bus structure for digital systems

Data

Extern
Bus

Clock
R1 R2 Rk

R1in R 1 out R2in R 2 out Rkin Rk out

Control circuit
Function 54
2-bit bus connecting: 2 registers

55
Swapping operation

(2)
R1 R2

R1 R2 (3) Using register 3 for

(1)
temporary storage
R3

R 2 out  R 3in R 1 out  R 2in R 3 out  R 1in

w D Q D Q D Q

Clock Q Q Q

Reset 56
 Verilog for swapping

Data

regn Extern
Bus

Clock
R1 R2 Rk

trin
R1in R 1 out R2in R 2 out Rkin Rk out

shiftr

Control circuit
Function 57
N-bit register module

module regn (R, Rin, Clock, Q);

parameter n = 8;
input [n-1:0] R;
input Rin, Clock;
output [n-1:0] Q; R Q
reg [n-1:0] Q;
regn
 
Clock
always @(posedge Clock)
if (Rin)
Q <= R;
Rin
endmodule 
58
Tri-state module

module trin (Y, E, F);

parameter n = 8;
input [n-1:0] Y;
input E;
output [n-1:0] F; Y F
trin
wire [n-1:0] F;
 
assign F = E ? Y : 'bz;
E
endmodule

59
 Control circuit module

module shiftr (Resetn, w, Clock, Q);

parameter m = 4;
input Resetn, w, Clock;
output [1:m] Q;
reg [1:m] Q;
integer k;
 
always @(negedge Resetn or posedge Clock)
if (!Resetn) Q[1] Q[2] Q[3] Q[4]
Q <= 0;
w
else
begin
for (k = m; k > 1; k = k-1)
Q[k] <= Q[k-1];
Q[1] <= w;
end
endmodule 60
 A digital system for swap

module swap (Data, Resetn, w, Clock, assign Rin[1] = RinExt[1] | Q[3];

Extern, RinExt, BusWires); assign Rin[2] = RinExt[2] | Q[2];
assign Rin[3] = RinExt[3] | Q[1];
input [7:0] Data; assign Rout[1] = Q[2];
input Resetn, w, Clock, Extern; assign Rout[2] = Q[1];
input [1:3] RinExt; assign Rout[3] = Q[3];
output [7:0] BusWires;  
tri [7:0] BusWires; regn reg_1 (BusWires, Rin[1], Clock, R1);
wire [1:3] Rin, Rout, Q; regn reg_2 (BusWires, Rin[2], Clock, R2);
wire [7:0] R1, R2, R3; regn reg_3 (BusWires, Rin[3], Clock, R3);
   
shiftr control (Resetn, w, Clock, Q); trin tri_ext (Data, Extern, BusWires);
defparam control.m = 3; trin tri_1 (R1, Rout[1], BusWires);
  trin tri_2 (R2, Rout[2], BusWires);
trin tri_3 (R3, Rout[3], BusWires);
 
endmodule
Q[1]: R2 out  R 3in
Q[2]: R 1 out  R 2in
Q[3]: R 3 out  R 1in Not supported in MAX+plusII 61
Swap based on multiplexers

Bus

R 1in R 2in Rkin

R1 R2 Rk

Clock

Data
S0
Multiplexers
Sj – 1

Control circuit
62
 Swap using multiplexers

regn reg_1 (BusWires, Rin[1], Clock, R1);

module swapmux (Data, Resetn, w, Clock,
regn reg_2 (BusWires, Rin[2], Clock, R2);
RinExt, BusWires);
regn reg_3 (BusWires, Rin[3], Clock, R3);
input [7:0] Data;
input Resetn, w, Clock;
always @(Q or Data or R1 or R2 or R3)
input [1:3] RinExt;
begin
output [7:0] BusWires;
if (Q == 3'b000) BusWires = Data;
reg [7:0] BusWires;
else if (Q == 3'b100) BusWires = R2;
wire [1:3] Rin, Q;
else if (Q == 3'b010) BusWires = R1;
wire [7:0] R1, R2, R3;
else BusWires = R3;
end
shiftr control (Resetn, w, Clock, Q);
 
defparam control.m = 3;
endmodule
 
assign Rin[1] = RinExt[1] | Q[3];
assign Rin[2] = RinExt[2] | Q[2];
assign Rin[3] = RinExt[3] | Q[1];

Q[1]: R 2 out
Q[1]: R2 out  R 3in
Q[2]: R 1 out
Q[2]: R 1 out  R 2in Q [1:3]: Q[1], Q[2], Q[3] Q[3]: R 3 out
Q[3]: R 3 out  R 1in 63
Simulation

64
Sequential circuit blocks
Desgin Examples

65
Sequential circuit blocks

Design examples:
1) Reaction timer
2) Ring counter
3) Linear-feedback shift register
Functionality of reaction timer

• To measure the reaction time of a person

to a specific event.
– the circuit turns on a LED.
– In response to the LED being turned on, the
person attempts to press a switch as quickly
as possible.
– The circuit measures the elapsed time from
when the LED is turned on until the switch is
pressed.

67
Specifications

• Available clock: 102.4 kHz

• Resolution of time measurement: 1/100 second
• Two-digit BCD display: 00/100 to 99/100 second
• Assume that a signal w is used to turn on the
LED.
• Push-button switch is depressed by a person to
generate a signal to turn off the LED.
• A counter will count the time between turn-on
and turn-off.

68
100 Hz clock

100 Hz
c9 c1 c0

clock 10-bit counter

102.4 KHz

69
The complete timer circuit

Digit1 Digit0
LEDn

pushn
w

c9

reset

70
Verilog code: 7-segment code

module seg7 (bcd, leds);

7-segment code input [3:0] bcd;
output [1:7] leds;
reg [1:7] leds;
seg7 always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
BCD code 2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
Combinational circuit 6: leds = 7'b1011111;
7: leds = 7'b1110000;
8: leds = 7'b1111111;
9: leds = 7'b1111011;
default: leds = 7'bx;
endcase
endmodule  71
Two-digit BCD counter

Function: output – 2 four-bit signal BCD1 and BCD0

clear– synchronous reset for both digits
E=1 – count on positive clock edge
E=0 – count value is unchanged.

BCD1

clear
BCD counter BCD0
E

clock

72
Verilog code: BCD counter

module BCDcount (Clock, Clear, E,

BCD1, BCD0); else if (E)
input Clock, Clear, E; if (BCD0 == 4'b1001)
output [3:0] BCD1, BCD0; begin
reg [3:0] BCD1, BCD0; BCD0 <= 0;
if (BCD1 == 4'b1001)
always @(posedge Clock) BCD1 <= 0;
begin else
if (Clear) BCD1 <= BCD1 + 1;
begin end
BCD1 <= 0; else
BCD0 <= 0; BCD0 <= BCD0 + 1;
end end
 
endmodule

73
 Verilog code: reaction timer
module reaction (c9, Reset, w, Pushn, LEDn, Digit1, Digit0);
input c9, Reset, w, Pushn;
output LEDn;
output [1:7] Digit1, Digit0;
wire LEDn;
wire [1:7] Digit1, Digit0;
reg LED;
wire [3:0] BCD1, BCD0;
pushn
always @(posedge c9)
begin
if (Pushn == 0)
LED <= 0;
else if (w)
LED <= 1;
end
assign LEDn = ~LED;
BCDcount counter (c9, Reset, LED, BCD1, BCD0);
seg7 seg1 (BCD1, Digit1);
seg7 seg0 (BCD0, Digit0);
 
endmodule 
74
 Simulation

a Digit1: abc_defg
W (rising)LED on
counting Digit0: abc_defg
f g b
Person pushed the button stop counting 1: 011_0000
LED off 2: 110_1101
e c
Display the elapsed time (result of counting)
d
Common cathode
75
Ring counter

4-bit ring counter Q0Q1Q2Q3: 100001000010000110000100

76
Verilog code for ring counter

module ripplen (Resetn, Clock, Q);

parameter n = 8;
input Resetn, Clock;
output [n-1:0] Q;
reg [n-1:0] Q;
always @(posedge Clock)
if (!Resetn)
begin
Q[7:1] <= 0;
Q[0] <= 1;
end
else
Q <= {{Q[6:0]}, {Q[7]}};
endmodule

77
Linear-feedback shift register

D Q D Q D Q
q0 q1 q2

clock

Generates a sequence of pseudo-random numbers

78
Linear-feedback shift register

module lfsr(r,L,clock,q);
input [0:2] r;
input L, clock;
output [0:2] q;
reg [0:2] q;

always @ (posedge clock)

if(L)
q <= r;
else
q <= {q[2], q[0]^q[2], q[1]};
endmodule

79
quiz

module lfsr2(r,L,clock,q);
input [0:2] r;
input L, clock;
output [0:2] q;
reg [0:2] q;

always @ (posedge clock)

if(L)
q <= r;
else
q <= {q[2], q[0], q[1]^q[2]};
endmodule

1. Draw the circuit using D-flip flips, multiplexers, and xor gate(s)
2. What is the sequence after loading r=001?

80
Sequential circuits
Finite State Machines
Outline

• General diagram of FSMs

• Two types of FSMs: Moore and Mealy
• Comparison between Moore and Mealy
• Introduction to Verilog for FSMs

82
 Two types of FSMs

Moore-type
Combinational Z
Combinational Q
Flip-flops circuit
circuit
W

Clock

Mealy-type
Combinational Z
Combinational Q
Flip-flops circuit
circuit
W

Clock
83
 Example: 1-1 detector

1-1 detector: generate an output z=1 whenever a second w=1 is detected

in consecutive clock cycles

Moore-type Mealy-type

The output z be equal to 1 in the clock The output z be equal to 1 in the same
Cycle that follows the detection of the clock cycle when the second w=1 is
second w=1 detected

Clockcycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 0 1 0 0 1 1 0

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

w: 0 1 0 1 1 0 1 1 1 0 1
z: 0 0 0 0 1 0 0 1 1 0 0 84
Example: 1-1 detector

Moore-type Mealy-type

Reset
w = 1  z = 0

A B

w = 0  z = 0 w = 1  z = 1
w = 0  z = 0

Less states
85
Example: 1-1 detector

Moore-type Mealy-type

86
 Example: 1-1 detector

Moore-type Mealy-type

z
Y2 y2
D Q z

Q w D Q
y

Clock Q
Y1 y1
w D Q

Q Resetn

Clock
Resetn

Simpler, note that the function is not exact the same

87
Example: 1-1 detector

Timing diagram

Moore-type

A C
B

Mealy-type

A B

88
W=1
Example: control circuit for swapping

Moore-type Mealy-type

4 states 3 states 89
Example: control circuit for swapping

Mealy-type Present Next state Output z

state w= 0 w= 1 w= 0 w= 1
A A B 0 R2out,R3in
B C C R1out, R2in
C A A R3out, R1in,Done

By inspection
y3y2y1
A:0 0 1 Y1=wy1+y3 R2out=R3in=wy1
B:0 1 0
C:1 0 0 Y2=wy1 R1out=R2in=y2

One-hot Y3=y2 R3out=R1in=done=y3

3 states
90
 Example: control circuit for swapping

Moore-type Mealy-type

w R 1 in
Y1 y1
D Q
R 3 out
y1
Clock Q Done

R 1 out

R 2 in

Y2 y2
D Q

y2
Q

R 2 out

R 3 in

91
 Summary of FSMs

Most of tasks can be realized by Moore-type FSM, as well as by

Mealy-type FSM, although these two type FSMs don’t have the exact
same logic function

Compared to Moore-type FSMs, Mealy-type FSMs have following features:

1) Less states;
2) Quick response;
3) Usually, simpler circuit implementation.

92
FSM design by CAD tools

• Different ways of FSM design using CAD

tools:
– Derive circuits from a state diagram manually 
draw a schematic into CAD systems or HDL
code  simulate  implement in a chip
(e.g.PLD).
– Enter state diagram into CAD systems using a
graphical tool  automatically synthesize.
– Write HDL code for state diagram 
automatically synthesize. ()
93
Example: Verilog code for FSMs
module simple (Clock, Resetn, w, z); y: present state
input Clock, Resetn, w;
output z;
Y: next state
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
 
State assignment
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn or posedge Clock)
if (Resetn == 0)y <= A;
elsey <= Y;
Y y
// Define output Next state Output z
w Flip-flops
assign z = (y == C); circuit circuit
 
endmodule 94
clock resetn
Verilog template for Moore FSMs
module FSM_name (Clock, Resetn, input_signal, output_signal);
input Clock, Resetn, input_signal;
output output_signal;
reg [n:1] state_present, STATE_NEXT;
parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;
  3 parallel blocks:
// Define the next state combinational circuit
always @(input_signal or state_present)
1) always block:
case (state_present) combinational circuit for
STATE1: if (input_signal) STATE_NEXT = …; next state
else STATE_NEXT = …; 2) always block:
STATE2: if (input_signal) STATE_NEXT = …;
else STATE_NEXT = …; update states
…… 3) assign:
default: Y = n'bxx; combinational circuit for
endcase
output
// Define the sequential block
always @(negedge Resetn or posedge Clock)
if (Resetn == 0)y <= STATE1;
elsey <= Y;

// Define output
assign output_signal = ….;
 
endmodule 95
Finite state machines
Outline
• Three Verilog code styles for FSMs
• Verilog codes for Moore and Mealy
• Two examples
– Sequence detector
– Control circuit for swapping
• Design process by problem 8.9
– Specifications
– State diagram
– Code
– simulation

97
Verilog template for Moore FSMs
module FSM_name (Clock, Resetn, input_signal, output_signal);
input Clock, Resetn, input_signal;
output output_signal;
reg [n:1] state_present, STATE_NEXT;
parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;
  3 parallel blocks:
// Define the next state combinational circuit
always @(input_signal or state_present)
1) always block:
case (state_present) combinational circuit for
STATE1: if (input_signal) STATE_NEXT = …; next state
else STATE_NEXT = …; 2) always block:
STATE2: if (input_signal) STATE_NEXT = …;
else STATE_NEXT = …; update states
…… 3) assign:
default: STATE_NEXT = n'bxx; combinational circuit for
endcase
output
// Define the sequential block
always @(negedge Resetn or posedge Clock)
if (Resetn == 0)y <= STATE1; Y y
elsey <= Y; Next state Output z
w Flip-flops
circuit circuit
// Define output
assign output_signal = ….;
  clock resetn
endmodule 98
Example: sequence detector
module simple (Clock, Resetn, w, z); y: present state
input Clock, Resetn, w;
output z;
Y: next state
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
 
State assignment
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase

// Define the sequential block

always @(negedge Resetn or posedge Clock)
if (Resetn == 0)y <= A;
elsey <= Y;
Y y
// Define output Next state Output z
w Flip-flops
assign z = (y == C); circuit circuit
 
endmodule 99
clock resetn
Second Verilog template
module FSM_name (Clock, Resetn, input_signal, output_signal);
input Clock, Resetn, input_signal;
output output_signal;
reg [n:1] state_present, STATE_NEXT;
parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;
  2 parallel blocks:
// Define the next state combinational circuit
always @(input_signal or state_present)
1) always block:
begin combinational circuit for
case (state_present) next state
STATE1: if (input_signal) STATE_NEXT = …; output
else STATE_NEXT = …;
STATE2: if (input_signal) STATE_NEXT = …; 2) always block:
else STATE_NEXT = …; update states
……
default: STATE_NEXT = n'bxx;
endcase merge

// Define output
output_signal=….; Y y
end Next state Output z
w Flip-flops
// Define the sequential block circuit circuit
always @(negedge Resetn or posedge Clock)
if (Resetn == 0)y <= STATE1;
elsey <= Y; clock resetn
endmodule 100
Example: sequence detector
module simple (Clock, Resetn, w, z); y: present state
input Clock, Resetn, w;
output z;
Y: next state
reg z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
State assignment
 
// Define the next state combinational circuit
always @(w or y)
begin
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
// Define output
z = (y == C);
end
// Define the sequential block
Y y
always @(negedge Resetn or posedge Clock) Next state Output z
w Flip-flops
if (Resetn == 0)y <= A; circuit circuit
elsey <= Y;
101
endmodule clock resetn
Third Verilog template
module FSM_name (Clock, Resetn, input_signal, output_signal);
input Clock, Resetn, input_signal;
output output_signal; 2 parallel blocks:
reg [n:1] state; // don’t need state_present, STATE_NEXT; 1) always block:
parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;
  sequential circuit for
// Define the sequential block next state
and update
always @(negedge Resetn or posedge Clock)
2) assign block:
if (Resetn == 0) state <= STATE1;
else for output
case (state)
STATE1: if (input_signal) state < = …; assign cannot be put inside
else state < = …; the always block
STATE2: if (input_signal) state <= …;
else state < = …; merge
……
default: state <= n'bxx;
endcase
Y y
// Define output Next state Output z
w Flip-flops
assign output_signal=….; circuit circuit

clock resetn
endmodule 102
 Example: sequence detector
module simple (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg [2:1] y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the sequential block
always @(negedge Resetn or posedge Clock)
if (Resetn == 0) y <= A;
else
case (y)
A: if (w) y <= B;
else y <= A;
B: if (w) y <= C;
else y <= A;
C: if (w) y <= C;
else y <= A;
default: y <= 2'bxx;
endcase
 
// Define output
assign z = (y == C);
endmodule
103
Summary of Verilog for FSMs

• No standard way for writing code that

represents an FSM.
• However, there are 3 templates we can
use to code, based on state diagram.
• The 3 templates provide identical
functionality, but may produce different
circuits.
• The first two templates are recommended.
• Similar templates exist for Mealy FSMs
104
 Example: control of swapping
module control (Clock, Resetn, w, R1in, R1out,
R2in, R2out, R3in, R3out,Done);
input Clock, Resetn, w;
output R1in, R1out, R2in, R2out,
R3in, R3out, Done;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01,
C = 2'b10, D = 2'b11;
 
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: Y = C;
C: Y = D; // Define outputs
D: Y = A; assign R2out = (y == B);
endcase assign R3in = (y == B);
assign R1out = (y == C);
// Define the sequential block assign R2in = (y == C);
always @(negedge Resetn or posedge Clock) assign R3out = (y == D);
if (Resetn == 0) y <= A; assign R1in = (y == D);
else y <= Y; assign Done = (y == D); 105
endmodule
Verilog for Mealy FSMs

• Similar to Moore FSMs

• The main difference between Mealy and Moore:
– For Moore, the output is defined independent of
inputs, so the code for output is separated from the
code for state transitions, e.g. case
– For Mealy, the code for output is written within the
case statement that also defines the state transitions.
• Two parallel blocks:
– always @ (inputs or current_states) defines the next
state and output.
– alwasy @ (negedge resetn or posedge clock) defines
flip-flops.

106
 Example: Verilog for Mealy
module mealy (Clock, Resetn, w, z);
input Clock, Resetn, w;
output z;
reg y, Y, z; // Define the sequential block
parameter A = 0, B = 1; always @(negedge Resetn or posedge Clock)
// Define the next state and output if (Resetn == 0) y <= A;
//combinational circuits else y <= Y;
always @(w or y)  
case (y) endmodule 
A: if (w)
begin
z = 0; Y = B;
end
else
begin
z = 0; Y = A;
Reset
end w = 1  z = 0
B: if (w)
begin
z = 1; Y = B; A B
end
else
begin w = 0  z = 0 w = 1  z = 1
w = 0  z = 0
z = 0; Y = A;
end
endcase
107
Verilog template for Mealy FSMs
module FSM_name (Clock, Resetn, input_signal, output_signal);
input Clock, Resetn, input_signal;
output output_signal;
reg [n:1] state_present, STATE_NEXT;
parameter [n:1] STATE1 = 2'b00, STATE2 = 2'b01…. ;
 
2 parallel blocks:
// Define the next state combinational circuit and outputs 1) always block:
always @(input_signal or state_present) combinational circuit for
case (state_present) next state and output
STATE1: if (input_signal) define output and next state;
else define output and next state; 2) always block:
STATE2: if (input_signal) define output and next state; update states
else define output and next state;
……
default: define output and next state;
endcase

// Define the sequential block

always @(negedge Resetn or posedge Clock) y
if (Resetn == 0)y <= STATE1; Next state Y Output z
elsey <= Y; w Flip-flops
circuit circuit

endmodule clock resetn

108
 Design example: prob8.9

Problem 8.9 a sequential circuit has two inputs, w1 and w2, and an output, z.
Its function is to compare the input sequences on the two inputs. If w1 =w2 during
any four consecutive clock cycles, the circuit produces z=1; otherwise, z=0.
For example
w1: 0 1 1 0 1 1 1 0 0 0 1 1 0
w2: 1 1 1 0 1 0 1 0 0 0 1 1 1
z: 0 0 0 0 1 0 0 0 0 1 1 1 0

109
 Prob8.9: state diagram

W=1 resetn
w  w1  w2
A W1 != w2
Mealy FSM
W=0

W=1 B 1 equal

W=0

W=1 C 2 equal

W=0
W=1
D 3 equal

W=0 / z=1 4 equal 110

 Prob8.9: Verilog code
module prob8_9 (Clock, Resetn, w1, w2, z);
input Clock, Resetn, w1, w2;
output z;
reg z;
reg [2:1] y, Y;
wire w;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;
// Define the next state and output combinational circuits
assign w = w1 ^ w2;
always @(w or y)
case (y)
A: if (w) begin Y = A; z = 0; end
else begin Y = B; z = 0; end
B: if (w) begin Y = A; z = 0; end
else begin Y = C; z = 0; end
C: if (w) begin Y = A; z = 0; end
else begin Y = D; z = 0; end
D: if (w) begin Y = A; z = 0; end
else begin Y = D; z = 1; end
endcase

// Define the sequential block

always @(negedge Resetn or posedge Clock)
if (Resetn == 0) y <= A;
else y <= Y;
endmodule 111
Prob8.9: simulation

• Specify input signals w1 and w2:

– Assume that w1 and w2 may change their values only
after the positive edges of clock with a small delay.
– This assumption is reasonable because w1 and w2
most likely come from a circuit with the same clock.
– Otherwise, the simulation result may be not what you
expected.

112
Prob8.9: simulation

113
Prob8.9: simulation problem

If inputs are not specified appropriately.

W1, w2, clock change at the same time

confused

114
 Verilog
Functions and Tasks

115
 behavioral modeling

Verilog Functions and Tasks

• Function and tasks are subprograms
• Useful for code that is repetitive in module
• Add to module readability
• Tasks
– Like procedures in other languages
– Task are invoked as statement : add(ina, inb, out);
• Function
– Return a value based on its inpurs
– Used in expressions : assign mult_out = add(ina, inb);

116
 behavioral modeling

Differences
• Functions • Tasks
– Can enable another function – Can enable other tasks and
but not another task functions
– Always executes in zero – May execute in non-zero
simulation time simulation time
– Can not contain any delay, – May contain delay(#),
event, or timing control event(@), or timing control
statements statements (wait)
– Must have at least one input – May have zero or more input,
argument output or inout arguments
– Always return a single value – Do not return a value
– Can not have output or inout
arguments

117
Differences between… (cont’d)

• Both
– are defined in a module
– are local to the module
– can have local variables (registers, but not nets) and
events
– contain only behavioral statements
– do not contain initial or always statements
– are called from initial or always statements or other
tasks or functions

118
Differences between… (cont’d)

• Tasks can be used for common Verilog code

• Function are used when the common code
– is purely combinational
– executes in 0 simulation time
– provides exactly one output
• Functions are typically used for conversions and
commonly used calculations

119
Tasks
Tasks

• Keywords: task, endtask

• Must be used if the procedure has
– any timing control constructs
– zero or more than one output arguments
– no input arguments

121
Tasks (cont’d)

• Task declaration and invocation

– Declaration syntax

task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask

122
Tasks (cont’d)

• Task declaration and invocation

– Task invocation syntax
<task_name>;
<task_name> (<arguments>);
– input and inout arguments are passed into the
task
– output and inout arguments are passed back
to the invoking statement when task is
completed
123
Tasks (cont’d)

• I/O declaration in modules vs. tasks

– Both used keywords: input, output, inout
– In modules, represent ports
• connect to external signals
– In tasks, represent arguments
• pass values to and from the task

124
 behavioral modeling

Task
• Example
module tasks;
task add; definition of a task :
input a, b;
task <task name>;
output c;
reg R; <argument ports>
begin <declarations>
R=1; <statements>
if(a==b) c=1&R; endtask
else c=0;
end
endtask
initial begin: init1 invocation of a task :
<name of task> (<port list>);
reg p;
add(1, 0, p);
$display (“p= %b”, p);
end
endmodule 125
Task Examples - Use of input and output arguments

module operation; task bitwise_oper;

parameter delay = 10; output [15:0] ab_and, ab_or,
reg [15:0] A, B; ab_xor;
reg [15:0] AB_AND, AB_OR, AB_XOR; input [15:0] a, b;
begin
initial #delay ab_and = a & b;
$monitor( …); ab_or = a | b;
ab_xor = a ^ b;
initial end
begin endtask
…
end
endmodule
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end

126
 Task Examples
Use of module local variables

module sequence; task init_sequence;

reg clock; begin
clock = 1'b0;
initial end
begin endtask
…
end task asymmetric_sequence;
begin
initial #12 clock = 1'b0;
init_sequence; #5 clock = 1'b1;
#3 clock = 1'b0;
always #10 clock = 1'b1;
asymmetric_sequence; end
endtask

endmodule 127
Functions
Functions

• Keyword: function, endfunction

• Can be used if the procedure
– does not have any timing control constructs
– returns exactly a single value
– has at least one input argument

129
Functions (cont’d)

• Function Declaration and Invocation

– Declaration syntax:

function <range_or_type> <func_name>;

<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

130
Functions (cont’d)

• Function Declaration and Invocation

– Invocation syntax:
<func_name> (<argument(s)>);

131
Functions (cont’d)

• Semantics
– much like function in Pascal
– An internal implicit reg is declared inside the
function with the same name
– The return value is specified by setting that
implicit reg
– <range_or_type> defines width and type of the
implicit reg
• type can be integer or real
• default bit width is 1

132
 behavioral modeling

Function
• Example
module functions;
function [1:1] add2;
definition of a function :
input a, b;
reg R; task <range or type><function name>;
begin <argument ports>
R=1; <declarations>
if(a==b) c=1&R; <statements>
else c=0; endtask
end
endfunction
initial begin: init1 invocation of a function :
reg p; value = <name of function> (<port list>);
p = add2(1,0);
$display (“p= %b”, p);
end
endmodule
133
Function Examples - Parity Generator

module parity; function calc_parity;

reg [31:0] addr; input [31:0] address;
reg parity; begin
calc_parity = ^address;
Initial begin end
… endfunction
end
endmodule
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end

134
Function Examples - Controllable Shifter

module shifter; function [31:0] shift;

`define LEFT_SHIFT 1'b0 input [31:0] address;
`define RIGHT_SHIFT 1'b1 input control;
reg [31:0] addr, left_addr, begin
right_addr; shift = (control==`LEFT_SHIFT) ?
reg control; (address<<1) : (address>>1);
end
initial endfunction
begin
… endmodule
end

always @(addr)begin
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
end

135
Tasks and functions – Summary

• Tasks and functions in behavioral modeling

– The same purpose as subroutines in SW
– Provide more readability, easier code management
– Are part of design hierarchy
– Tasks are more general than functions
• Can represent almost any common Verilog code
– Functions can only model purely combinational
calculations

136