• The Intel 8253 is a programmable counter /

timer chip designed for use as an Intel

microcomputer peripheral. It uses N-MOS
technology with a single +5V supply and is
packaged in a 24-pin plastic DIP.
• It is organized as 3 independent 16-bit
counters, each with a counter rate up to 2
MHz . All modes of operation are software
programmable.
• Clock This is the clock input for the counter.
The counter is 16 bits. The maximum clock
frequency is 1 / 380 nanoseconds or 2.6
megahertz. The minimum clock frequency is
DC or static operation.
• Out This single output line is the signal that
is the final programmed output of the
device. Actual operation of the out line
depends on how the device has been
programmed.
• Gate This input can act as a gate for the clock
input line, or it can act as a start pulse,
depending on the programmed mode of the
counter.
Block diagram of 8253
Data Bus Buffer :
• This tri-state, bi-directional, 8-bit buffer is used to interface the 8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic : The Read/Write logic has five signals : RD, WR, CS and the
• address lines A0 and A1. In the peripheral I/O mode, the RD, and WR signals are
connected to IOR and IOW, respectively. In memory-mapped I/O, these are
connected to MEMR and MEMW. Address lines A0 and A1 of the CPU are usually
connected to lines A0 and A1 of the 8253/54, and CS is tied to a decoded address.
The control word register and counters are selected according to the signals on
lines A0 and A1.
Control Word Register :
This register is accessed when lines A0 and A1 are at logic 1. It is used to
write a command word which specifies the counter to be used (binary or
BCD), its mode, and either a read or write operation.
Counters :
These three functional blocks are identical in operation. Each counter
• consists of a single, 16 bit, pre-settable, down counter. The counter can
operate in either binary or BCD and its input, gate and output are
configured by the selection of modes stored in the control word register.
The counters are fully independent. The programmer can read the
contents of any of the three counters without disturbing the actual count
in process.
Programming the 8253/54 :
• Each counter of the 8253/54 is individually programmed by writing a control word
into the control word register (A0 - A1 = 11).
WRITE Operation :
1. Write a control word into control register.
2. Load the low-order byte of a count in the counter register.
3. Load the high-order byte of count in the counter register.
READ Operation :
In some applications, especially in event counters, it is necessary to read the value
of the count in process. This can be done by two possible methods:
1. Simple Read :
It involves reading a count after inhibiting the counter by controlling the gate
input or the clock input of the selected counter, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
2. Counter Latch Command :
In the second method, an appropriate control word is written into the control
register to latch a count in the output latch, and two I/O read operations are
performed by the CPU. The first I/O operation reads the low-order byte, and the
second I/O operation reads the high order byte.
 MODES OF 8253
• Mode 0 : Interrupt on terminal count
• MODE 1 : Hardware Retrigger able One-shot
• MODE 2 : Rate generator
• MODE 3 : Square Wave Rate Generator
• MODE 4 : Software Triggered Strobe.
• MODE 5 : Hardware triggered strobe (Retrigger able).
 Mode 0 : Interrupt on terminal count

• 1) The output will be initially low after the mode set operation.
• 2) After the count is loaded into the selected count Register the output
will remain low and the counter will count.
• 3) When the terminal count is reached the output will go high and
remain high until the selected count is reloaded.
• 1)Gate = 1 enables counting.
• 2) Gate = 0 disables counting.
 Let us set channel 0 in mode 0
START: MVI A, 30
OUT 0CEH
MVI A, 05
OUT 0C8H
MVI A, 00
OUT 0C8H
HLT

Observe, using an CRO that the output of channel 0 is initially low. After giving six clock
pulse the output goes high
 MODE 1 : Hardware Retrigger able One-shot

a) Normal operation
1) The output will be initially high
2) The output will go low on the CLK pulse following the rising edge at the
gate input.
3) The output will go high on the terminal count and remain high until the
next rising edge at the gate input.
b) Retriggering
The one shot is retrigger able, hence the output will remain low for the
full count after any rising edge of the gate input.
c) New count
If the counter is loaded during one shot pulse, the current one shot is not
affected unless the counter is retriggered. If retriggered, the counter is
loaded with the new count and the one-shot pulse continues until the
new count expires.
START: MVI A, 32
OUT 0CEH
MVI A, 05
OUT 0C8H
MVI A, 00
OUT 0C8H
OUT 0D0H ;triggers gate 0
HLT
 MODE 2 : Rate generator
This mode functions like a divide by-N counter.
a) Normal Operation
1) The output will be initially high.
2) The output will go low for one clock pulse before the terminal count.
3) The output then goes high, the counter reloads the initial count and the
process is repeated.
4) The period from one output pulse to the next equals the number of input
counts in the count register.
b) Gate Disable
1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).
2) If Gate goes low during an low output pulse, output is set immediately
high. A trigger reloads the count and the normal sequence is repeated.
c) New count The current counting sequence does not affect when the new
count is written. If a trigger is received after writing a new count but
before the end of the current period, the new count will be loaded with
the new count on the next CLK pulse and counting will continue from the
new count. Otherwise, the new count will be loaded at the end of the
current counting cycle.
Using mode 2, divide the clock preset
at channel 1 by 10
START: MVI A, 74
OUT 0CEH ;channel 1 in mode 2
MVI A, 0AH ;LSB of count
OUT 0CAH
MVI A, 00H ;MSB of count
OUT 0CAH
HLT
Mode 3 Square Wave Rate Generator
a)Normal operation
1) Initially output is high.
2) For even count, counter is decremented by 2 on the falling edge of each clock pulse. When the
counter reaches terminal count, the state of the output is changed and the counter is
reloaded with the full count and the whole process is repeated.
3) If the count is odd and the output is high the first clock pulse (after the count is loaded)
decrements the count by 1. Subsequent clock pulses decrement the clock by 2. After timeout,
the output goes low and the full count is reloaded. The first clock pulse (following the reload)
decrements the count by 3 and subsequent clock pulse decrement the count by two. Then
the whole process is repeated. In this way, if the count is odd, the output will be high for
(n+1)/2 counts and low for (n-1)/2 counts.
b) Gate Disable
If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while output is low,
output is set high immediately. After this, When Gate goes high, the counter is loaded with
the initial count on the next clock pulse and the sequence is repeated.
c) New Count
The current counting sequence does not affect when the new count is written. If a trigger is
received after writing a new count but before the end of the current half-cycle of the square
wave, the counter will be loaded with the new count on the next CLK pulse and counting will
continue from the new count. otherwise, the new count will be loaded at end of the current
half-cycle.
 To generate a square wave of
frequency 150 KHz at channel
START: MVI A, 36
OUT 0CEH
MVI A, 0A
OUT 0C8H
MVI A, 00
OUT 0C8H
HLT
Vary the frequency by varying the count . Here the maximum count is FFFF. Thus with
the clock frequency of 1.5 MHZ, which corresponds to 0.6 micro sec
 MODE 4 : Software Triggered Strobe
a) Normal operation
1) The output will be initially high
2) The output will go low for one CLK pulse after the terminal count (TC).
3) And become high again
b) Gate Disable
• If Gate is one the counting is enabled otherwise it is disabled. The Gate
has no effect on the output.
c) New count
• If a new count is written during counting, it will be loaded on the next CLK
pulse and counting will continue from the new count. If the count is two
byte then
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be loaded on the next CLK
pulse.
 MODE 5 : Hardware triggered strobe
Retriggerable
a) Normal operation
• 1) The output will be initially high.
• 2) The counting is triggered by the rising edge of the Gate.
• 3) The output will go low for one CLK pulse after the terminal count (TC).
b) Retriggering
If the triggering occurs on the Gate input during the counting, the initial count is
loaded on the next CLK pulse and the counting will be continued until the terminal
count is reached.
• c) New count
• If a new count is written during counting, the current counting sequence will
not be affected. If the trigger occurs after the new count is written but before the
terminal count, the counter will be loaded with the new count on the next CLK
pulse and counting will continue from there.