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Microprocessor and Assembly Language CSC-321: Sheeza Zaheer

The document discusses logic instructions in assembly language including AND, OR, XOR, NOT, and TEST. It provides truth tables for AND, OR, and XOR. It explains how to use masks with AND, OR, and XOR to selectively clear, set, or complement bits in a destination. Examples are given to clear flags, convert between ASCII and numeric values, change case for letters, clear a register, test a register for zero, and examine individual bits.

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ali chaudary
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67 views

Microprocessor and Assembly Language CSC-321: Sheeza Zaheer

The document discusses logic instructions in assembly language including AND, OR, XOR, NOT, and TEST. It provides truth tables for AND, OR, and XOR. It explains how to use masks with AND, OR, and XOR to selectively clear, set, or complement bits in a destination. Examples are given to clear flags, convert between ASCII and numeric values, change case for letters, clear a register, test a register for zero, and examine individual bits.

Uploaded by

ali chaudary
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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1

Microprocessor and Assembly


Language
CSC-321
Sheeza Zaheer
Lecturer
COMSATS UNIVERSITY ISLAMABAD
LAHORE CAMPUS
2

Logic Instructions
OUTLINE
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● Logic Instructions
■ AND
■ OR
■ XOR
■ NOT
■ TEST

● References
■ Chapter 7, Section 7.1, Ytha Yu and Charles Marut,
“Assembly Language Programming and Organization of
IBM PC
Logic Instructions
4
● To manipulate individual bits
● Binary Value 0 treated as false
● Binary Value 1 treated as true
● In Assembly Language:
■ AND
■ OR
■ XOR
■ NOT
■ TEST
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Truth Tables
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a b a AND b a OR b a XOR b
0 0 0 0 0
0 1 0 1 1
1 0 0 1 1
1 1 1 1 0

a NOT a
0 1
1 0

5
Examples
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Syntax
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AND destination, source
OR destination, source
XOR destination, source
● Destination:
■ Stores result
■ Can be Register or Memory Location
● Source:
■ May be a Constant, Register or Memory Location
● Memory to memory operation not allowed
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Effects on Flags
8

● SF, ZF, PF reflects the result


● AF is undefined
● CF, OF = 0

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MASK
9
● To modify only selective bits in destination, we construct a
source bit pattern known as MASK.
● To choose mask, use following properties:
■ b AND 1 = b (e.g. 0 AND 1 = 0 , 1 AND 1 = 1)
■ b AND 0 = 0 (e.g. 0 AND 0 = 0 , 1 AND 0 = 0)
■ b OR 1 = 1 (e.g. 0 OR 1 = 1 , 1 OR 1 = 1)
■ b OR 0 = b (e.g. 0 OR 0 = 0 , 1 OR 0 = 1)
■ b XOR 0 = b (e.g. 0 XOR 0 = 0 , 1 XOR 0 = 1)
■ b XOR 1 = ~b (complement of b) (e.g. 0 XOR 1 = 1 , 1
XOR 1 = 0)
Where b represents a bit (0 or 1)

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AND Instruction
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The AND instruction:


- May be used to clear specific destination bits
while preventing the others.
- A 0 mask bit clears the corresponding
destination bit.
- A 1 mask bit preserves the corresponding
destination bit.

10
Example 1
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● Clear the sign bit of AL while leaving the
other bits unchanged.
● Solution:
AND AL, 7Fh
Where 7Fh (0111 1111) is the mask.
Suppose,
AL = 1000 1010
AND 0111 1111
0000 1010
11
OR Instruction
12
The OR instruction:
- May be used to set specific destination bits
while preventing the others.
- A 1 mask bit sets the corresponding
destination bit.
- A 0 mask bit preserves the corresponding
destination bit.

12
Example 2
13
● Set the MSB and LSB of AL while
preserving the other bits.
● Solution:
OR AL, 81h
Where 81h (1000 0001) is the mask.
Suppose,
AL = 1000 1010
OR 1000 0001
1000 1011
13
XOR Instruction
14
The XOR instruction:
- May be used to complement specific
destination bits while preventing the others.
- A 1 mask bit complements the corresponding
destination bit.
- A 0 mask bit preserves the corresponding
destination bit.

14
Example 3
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● Change the sign bit of DX.
● Solution:
XOR DX, 8000h
Where 80h (1000 0000) is the mask.

Suppose,
DX = 1000 1010 0001 1011
XOR 1000 0000 0000 0000
15
0000 1010 0001 1011
Converting an ASCII digit to a
Number
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● ASCII code for digit “0-9” is “30h-39h”
AND AL, CFh ;Clears the high nibble.
Suppose,
AL = 0011 0101
AND 1100 1111
0000 0101

● How to convert decimal digit to ASCII code?

16
Converting a Lowercase letter to Uppercase
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● Lower case: 61h to 7Ah
● Uppercase: 41h to 5Ah
● Lower to upper case, only clear bit 5. So, the
mask is 1101 1111b (0DFh)
AND DL, 0DFh
Suppose,
DL = 0110 0101
AND 1101 1111
0100 0101
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Clearing a Register
18

MOV AX, 0 ;machine code 3 bytes


OR
SUB AX, AX ;machine code 2 bytes
OR
XOR AX, AX ;machine code 2 bytes

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Testing a Register for zero
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CMP CX, 0
Is same like:
OR CX, CX ;sets ZF = 1 if CX is 0

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NOT Instruction
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● Performs the one’s complement operation on
the destination.
● Syntax:
NOT destination
● No effect on flags
● Example: Complement the bit in AX:
NOT AX

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TEST Instruction
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● Performs an AND operation without changing
destination i.e. only status flags updated.
● Syntax:
TEST destination, source
● Effects on flags:
■ SF, ZF and PF reflects the results
■ AF is undefined
■ CF, OF = 0

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Contd..
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● Examining the individual bits:
TEST destination, mask
● If destination have all zero, then ZF = 1
● The tested bit position is 1 if and only if corresponding source bit is 1
● Example: Jump to label BELOW if AL contains an even number.
● Solution: Even numbers have 0 at bit 0 so the mask is 0000 0001
TEST AL, 1
JZ BELOW
e.g.
2= 0010, 3 = 0011, 4 = 0100, 5 = 0101, 6 = 0110, 7 = 0111
Suppose,
AL = 0111 0100
AND 0000 0001
0000 0000
22

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