What is a

program?

arithmetic or
logical operation
is done
a different set of
control signals is
needed

2
 Computer
Components PC =
Central Processing Unit Computer
(CPU) Program
Syste Counter
Main
PC MAR m . IR =
MB Memory
.
IR Bus 0
R Instruction
I/O Instruction 1 Register
Execution 2
AR Instruction MAR = Memory
Unit I/O .
.
BR . . Address
Data . Register MBR =
I/O Data Memory
Module Buffer Register
.
. I/O AR =
. Input/Output
Buffer
Address
s
Register
3
I/O BR =
 Instruction
• Two steps Cycle
 Fetch cycle
 Execute
cycle Fetch Execution
cycle cycle

Fetch Next Execute

Star Hal
Instructio
t t
Instructio n
n

4
 Fetch
Cycle
Progra Instruction
m Processor Processor
Register
Counter
(IR)
(PC) • Fetch • Load the • Interprets
• Holds instruction from instruction instruction
address of memory • Perform
next location pointed required
instruction to to by PC actions
fetch • Increment PC

5
 Instruction Cycle: Fetch
Cycle

• Holds address of
Processor • Load the instruction
Processor
next instruction to
• Fetch instruction • Interprets instruction
fetch
from memory • Perform required
location pointed to actions
by PC
• Increment PC
Program Instruction
Counter Register
(PC) (IR)

6
 Program Execution -
Example Memory CPU
Registers
Address Instruction Address P
C
Addres Instruction Data A
C
s Instruction Instruction I
Addres R
…
s
Address Data
Address Data

CSNB123 Computer Organization |

1_2017/2018 Systems 7
& Networking | UNITEN
 Program Execution – Fetch
Cycle • Step 1: Program
Memory CPU Counter (PC) – provide
Registers
Instruction Address
address next
Address P
Instruction Data
C
A
instruction
Addres
s Instruction Instruction
C
I
• Step 2: Processor – Refer
Addres …
R to Address. Fetch
s
Address Dat instruction. Increment
Address a
Dat PC
a
• Step 3: Instruction
Register (IR) –
load fetched
instruction
1_2017/2018
• Step
CSNB123 Computer Organization | 4: Processor 8
Systems
& Networking | UNITEN
 Program Execution – Execute
Cycle • Follow the
Memory CPU
Registers analyzed
Address Instruction Address+1 P instruction
C
Addres Instruction Data A
C • Operation to be
s Instruction Instruction
Addres … done maybe:
IR
s
Address Data  Arithmetic operation
Address Data
 Data movement from
memory into AC or
from AC into memory

CSNB123 Computer Organization |

1_2017/2018 Systems 9
& Networking | UNITEN
 Address
Memory
Instruction
Instruction
Addres Instruction
This chapter’s
s Instruction
Addres
•scope
Operation Codes
s refer in integer form
• Consists of 2 parts: • Common
operation code:

X XX
 1 – Move data
from memory to
AC
 2 – Move data
from

X
AC to memory
Operatio Memor  5 – Perform
Addition between
n y content in AC and
Code Address memory address
CSNB123 Computer Organization |
1_2017/2018 Systems 10
& Networking | UNITEN
 Program Execution –
Example
Fetch Step 1: Program
Cycle Counter (PC) – provide
Memor CPU
address next
y Registers instruction
300 1940
194 300 P
0 C • PC = 300
301 5941 A
C
302 2941 I
R
…
940 0003
941 0002

CSNB123 Computer Organization |

1_2017/2018 Systems 11
& Networking | UNITEN
 Program Execution –
Example
Fetch Step 2: Processor –
Cycle Refer to Address.
Memor CPU
Fetch instruction.
y Registers Increment PC
300 194
1940 300 PC
0 • Go to address
301 5941 AC
302 2941 IR 300
… • Fetch
940 0003
941 0002
instruction
1940 to IR
• Increment PC
CSNB123 Computer Organization |
1_2017/2018 Systems 12
& Networking | UNITEN
 Program Execution –
Example
Fetch Step 3: Instruction
Cycle Register (IR) –
Memory CPU
load fetched
Registers instruction
300 1940
194 301 P
0
5941
C
A
• Load instruction
301
302 2941 1940
C
I 1940 into IR
R
…
940 0003
941 0002

CSNB123 Computer Organization |

1_2017/2018 Systems 13
& Networking | UNITEN
 Program Execution –
Example
Fetch Step 4:
Cycle Analyze
Memory CPU
Instruction
• Instruction: 1940
Registers
300 1940 301 P
• Operation Code: 1
C
301 5941 A • Address: 940
C
302 2941 1940 I
…
R • Analysis: Load
940 0003 data from address
941 0002 940 into AC
--- End of Fetch cycle
--- CSNB123 Computer Organization |
1_2017/2018 Systems 14
& Networking | UNITEN
 Program Execution –
Example
Execution • Execution: Load
Cycle data from address
Memory CPU
940 into AC
Registers
300 1940 30
301 P
0 C
301 5941 0003 A
C
302 2941 1940 I
R
…
940 0003
000
3
941 0002

--- End of Execution cycle

--- CSNB123 Computer Organization |
1_2017/2018 Systems 15
& Networking | UNITEN
 Program Execution –
Example
Fetch Execution
Cycle Cycle
Memory CPU Registers Memory CPU Registers
300 1940 PC 300 301
194 300 1940 30
0 0
5941 PC

301 5941 AC 301 0003

1940 2941

AC
302 2941 IR 302 000 1940
3
IR
… …
Analysis: Execution:
940 0003 Load data from 940 0003 0003 loaded into
941 0002 940 into AC 941 0002 AC
CSNB123 Computer Organization |
1_2017/2018 Systems 16
& Networking | UNITEN
 Program Execution –
Example
Fetch Execution
Cycle Cycle
Memory CPU Registers Memory CPU Registers
300 302 PC
300 1940 301 P 1940 30
301 1
0005 AC
301 5941
594 0003 C 5941 0003
1 A 302
302 2941 5941 IR
5941 2941
… C … Execution:
940 0003 IR 940 0003 0003 + 0002 =
941 0002 0005
941 0002 Analysis: Store result into
Perform ADD AC
operation
between AC and
941

CSNB123 Computer Organization |

1_2017/2018 Systems 17
& Networking | UNITEN
 Program Execution –
Example
Fetch Execution
Cycle Cycle
Memory CPU Registers Memory CPU Registers
300 1940 PC
301 5941 302 AC 300 1940 303
30 P
302 1 C
2941 0005 IR 301 5941 0005
… 302 A
294 Analysis:
2941 2941 2941
940 0003
1 Load data from … C
941 0002 AC into 941
940 000 IR
941 3 Execution:
000
0005
2 Load 0005 from
AC into
address 941

CSNB123 Computer Organization |

1_2017/2018 Systems 18
& Networking | UNITEN
 Program Execution – Overall
view

CSNB123 Computer Organization |

1_2017/2018 Systems & Networking | 19
 Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing

20
 Interrupt
• Cycle
Added to instruction
cycle Fetch Execution Interrupt
cycle cycle cycle
Interrupt
s
disabled
Check for
Fetch Next Execute
Star interrupt; process
Instructio Interrupt
t interrupt
Instructio n s
n enabled

Hal
t

21
 Interrupt Cycle
• (Cont.)
Processor checks for interrupt
 Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler
routine
 Process interrupt
 Restore context and continue interrupted
22
program
 Interconnection
• Structures
Collection of paths connecting the
various modules
• Modules:
 Memory
 Processor
 I/O module

23
 Modules: Major Form of Input
and Output - Memory
• Word of data - Read
from or written into the
memory
 Assigned a
unique numerical
address
• Nature of the operation
– indicated by read and
write control signals
• Address – specify the
location for the
operation
24
 Modules: Major Form of Input
and Output - Processor
• Reads instruction
and data
• Writes out data
(after processing)
• Sends control signals
to other units
• Receives (& acts
on) interrupts

25
 Modules: Major Form of Input
and Output – I/O Module
• Operations;
 Read
 Write
• Control more than
one external device
• External data path –
input and output of data
• Send interrupt signals
to CPU

26
 Modules:
Major Form of Input and
Output

27
 Types of
• Memory toTransfers
processor: Processor
reads instruction/data from memory
• Processor to memory: Processor writes data
to memory
• I/O to processor: Processor reads data from
I/O device (via I/O module)
• Processor to I/O: Processor sends data to
I/O device
• I/O to/from memory: allowed to exchange
data using Direct Memory Access (DMA) –
exclude processor
28
 Bus
• Interconnection
Communication pathway connecting two
or more devices
• Key characteristic: shared
transmission medium
• Consists of multiple
communication pathways/lines
 Lines – transmit signals representing binary 1
and 0 – one data at a time

29
 System
• Bus major
A bus that connects
computer components (CPU,
memory, I/O)
• Computer interconnection structures –
use one or more system buses
• Consists of 50 to hundreds of separate
lines
 Each line – function. E.g: power

30
 Data
• Line
Provide a path for moving data among
system modules
• Collective – data bus

31
 Data
• Bus
Collective of data lines
• Width of the data bus - Number of lines;
 32, 64, 128 …
 Key factor in determining overall
system performance
• Number of data lines – represents number
of data can be transferred at a time

32
 Address
• Designate theLines
source or destination of
the data on data bus

33
 Address
• Bus lines
Collective of address
• Width of the address bus determines the
maximum possible memory capacity of
the system

34
 Control
• Lines
Used to control the access to and the use
of the data and address lines
• Control signals transmit both command
and timing information among system
modules
 Command signals – specify operations to
be performed
 Timing signals – validity of data and
address information
35
Bus Interconnection
Scheme

36
 Operation of the
• Bus
Send data
 Obtain the use of the bus
 Transfer data via the bus
• Request data
 Obtain the use of the bus
 Transfer a request to the other module
over appropriate control and address lines

37
 System Bus -
Physical
• Number of parallel
electrical conductors
– metal lines on the
circuit board

38
 Single Bus -
• Many ofProblem
devices on one bus leads to:
 Propagation delays
• Long data paths mean that co-ordination of bus use
can
adversely affect performance
• If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to
overcome these problems

39
 Types of
• Dedicated Bus
 Separate data & address lines
• Multiplexed
 Shared lines
 Address valid or data valid control
line
 Advantage
• Fewer lines
 Disadvantages
• More complex control
• Reduction in performance
40
 Bus
• Arbitration
Process of insuring only 1 devices
places information onto the bus at a
time

41
42