SCSA1402-COMPUTER ARCHITECTURE AND

ORGANIZATION
Unit - 1

8/6/2020 1
 C= A +B High level language

• Macro Level
• Get input from the input device
• Store it somewhere (Memory or register)
• Operation should be performed (Arithmetic or logic operations- correct operation should be selected)
• On the operands, the operation should be performed
• After performing operation, result should be stored somewhere
• This somewhere will be answered by COMPUTER ARCHITECTURE
• After getting the input, A value will be stored in one among the many registers
• Selection unit is responsible for selecting the register (Decoder or Multiplexer is used)
• After getting the input, B value will be stored in one among the many registers
• From the registers, using wires or data bus data will be transferred to the ALU for performing
arithmetic operations
• Again the result will be stored in any one of the registers
• Easy to explain in English, but machine will not understand
• A Control word, used for performing all these operations. By writing a set of sequences called a
control word, we could make the machine perform any operation that we require
• From Macro leve C=A+B, understanding it in micro level is dealt in computer architecture
 COURSE OUTCOMES
CO1 - Classify the various types of registers, microinstructions
and addressing modes.
CO2 - Design the data path for processor.
CO3 - Demonstrate the usage of Memory Organization.
CO4 - Describe about the I/O devices.
CO5 - Explain the characteristics, structure, communication and
synchronization of multiprocessor.
CO6 - State the inter processor communication and
synchronization.
 TEXT / REFERENCE BOOKS
1. M.Morris Mano, “Computer system Architecture”, 3rd Edition, Prentice-Hall
Publishers, 2007.
2. Mark Burrell, “Fundamentals of Computer Architecture”, Mcmillan Higher Education,
2003.
3. John D. Carpinelli, “Computer Systems Organization and Architecture”, Pearson
Education, 2001.
4. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, 5 th
Edition, McGraw-Hill, 2002.
5. William Stallings, “Computer Organization and Architecture - Designing for
Performance”, 9 th Edition, Prentice Hall, 2012.
6. John P Hayes, Computer Architecture Organization, McGraw Hill Edition 4, 2003.
COMPUTER LEVEL HIERARCHY

• Binary or Machine Language - 010110

• Assembly Language - MOV A,B
• High Level Language – C,C++,etc.
BLOCK DIAGRAM OF DIGITAL COMPUTER
 COMPUTER ARCHITECTURE
• Computer architecture is a specification detailing how a set of software and hardware
technology standards interact to form a computer system or platform.
• In short, computer architecture refers to how a computer system is designed and what
technologies it is compatible with.
• As with other contexts and meanings of the word architecture, computer architecture is
likened to the art of determining the needs of the user/system/technology, and creating
a logical design and standards based on those requirements.
• A very good example of computer architecture is von Neumann architecture, which is
still used by most types of computers today.
• This was proposed by the mathematician John von Neumann in 1945.
• It describes the design of an electronic computer with its CPU, which includes the
arithmetic logic unit, control unit, registers, memory for data and instructions, an
input/output interface and external storage functions.
 THE VON NEUMANN MODEL

Central Processing Unit (CPU)

• The Central Processing Unit (CPU) is the
electronic circuit responsible for executing the
instructions of a computer program.
• It is sometimes referred to as the microprocessor
or processor.
Registers
• Registers are high speed storage areas in the CPU.  All
data must be stored in a register before it can be
processed.

Holds the memory location of data that needs to be

MAR Memory Address Regi
ster accessed Arithmetic and Logic Unit (ALU)
• The ALU allows arithmetic (add,
MDR Memory Data Registe
r
Holds data that is being transferred to or from memory subtract etc) and logic (AND, OR,
NOT etc) operations to be carried
Where intermediate arithmetic and logic results are
AC Accumulator stored out.
Contains the address of the next instruction to be
PC Program Counter executed

CIR Current Instruction Re Contains the current instruction during processing

gister
 THE VON NEUMANN MODEL Contd.
Control Unit (CU)
• The control unit controls the operation of the Buses
computer’s ALU, memory and input/output devices, • Buses are the means by which data is
telling them how to respond to the program transmitted from one part of a computer to
instructions it has just read and interpreted from the another, connecting all major internal
memory unit. components to the CPU and memory.
• The control unit also provides the timing and • A standard CPU system bus is comprised
control signals required by other computer of a control bus, data bus and address bus.
components.
Carries the addresses of data (but not the
Address Bus
data) between the processor and memory
Memory Unit
• The memory unit consists of RAM, sometimes Data Bus
Carries data between the processor, the
memory unit and the input/output devices
referred to as primary or main memory.  Unlike a
hard drive (secondary memory), this memory is Carries control signals/commands from the
CPU (and status signals from other devices)
fast and also directly accessible by the CPU. Control Bus
in order to control and coordinate all the
activities within the computer
 FUNCTIONAL AND STRUCTURAL UNITS OF
A COMPUTER
There are four main functions of a computer:
• Data processing
• Data storage
• Data movement
• Control

Main Structural Blocks/Parts:

Central Processing Unit (CPU): Controls the operation of the computer and performs its
data processing functions. Often simply referred to as processor.

Main Memory: Stores data.

I/O: Moves data between the computer and its external environment.

System Interconnection: e.g. BUS for communication among CPU, main memory, and I/O.
 MAJOR STRUCTURAL COMPONENTS OF A CPU

Control Unit (CU): Controls the operation of the CPU and hence the
computer.

Arithmetic and Logic Unit (ALU): Performs computer’s data processing

functions.

Register: Provides storage internal to the CPU.

CPU Interconnection: communication among the control unit, ALU, and

register.
 CPU ORGANIZATION

The data path of a typical Von Neumann machine.

 THE VON NEUMANN MODEL

• This is a general
depiction of a von
Neumann system:

• These computers
employ a fetch-
decode-execute
cycle to run
programs as follows
...
 THE VON NEUMANN MODEL
Contd.
• The control unit fetches the next instruction from memory using the program
counter to determine where the instruction is located.
 THE VON NEUMANN MODEL
Contd.
• The instruction is decoded into a language that the ALU can understand.
 THE VON NEUMANN MODEL
Contd.
• Any data operands required to execute the instruction are fetched
from memory and placed into registers within the CPU.
 THE VON NEUMANN MODEL
Contd.
• The ALU executes the instruction and places results in registers or
memory.
Central Processing Unit (CPU)
CENTRAL PROCESSING UNIT (CPU)

Introduction
General Register Organization
Stack Organization
Reverse Polish Notation (RPN)
 MAJOR COMPONENTS OF CPU
CPU:
Central Processing Unit(CPU) is the part of the computer that
performs bulk data processing operation Register set
Components:
 ALU Control Unit (CU)
 Registers
 Control Unit Arithmetic Logic Unit

Arithmetic Logic Unit (ALU): (ALU

Performs the required micro operations for executing the instructions
Arithmetic calculations,
Logical computations,
Shifts/Rotates
Registers:
Stores intermediate date used during the execution of instructions
Control Unit :
Supervises the transfer of information among registers and instructs the ALU as to
which operation to perform
 GENERAL REGISTER ORGANIZATION
Memory is needed for storing
• Pointers
• Return address
• Temporary results
• Partial products during Multiplication
Disadvantage of memory
Memory access is the most time consuming operation in a computer
Register organization
• The more convenient and efficient way to store these intermediate values is
using registers
• The register communicate with each other not only for direct data transfer, but
 GENERAL REGISTER ORGANIZATIONS
Input
Clock

R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB

3x8
A bus B bus
decoder

SELD
OPR ALU

Output
 GENERAL REGISTER ORGANIZATIONS Contd.
• A bus organization for seven CPU registers is shown
• The output of each register is connected to two multiplexers (MUX) to form the two buses
A and B .
• The selection lines in each multiplexer select one register or the input data for the
particular bus.
• The A and B buses form the inputs to acommon arithmetic logic unit (ALU).
• The operation selected in the ALU determines the arithmetic or logic micro operation that
is to be performed.
• The result of the micro operation is available for output data and also goes into the inputs
of all the registers.
• The register that receives the information from the output bus is selected by a decoder.
• The decoder activates one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.
 GENERAL REGISTER ORGANIZATIONS Contd.
R1 ←R2 + R3
Input
Clock

R1 R2
R2
R3
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
010 011
3x8
A bus B bus
decoder

001 SELD
OPR ALU
00010

Output
 CONTROL WORD
• There are 14 binary selection inputs in the unit, and their combined value specifies a
control word.
• It consists of four fields.
• Three fields contain three bits each, and one field has five bits.
• The three bits of SELA select a source register for the A input of the
• ALU.
• The three bits of SELB select a register for the B input of the ALU.
• The three bits of SELD select a destination register using the decoder and its seven
load outputs.
• The five bits of OPR select one of the operations in the ALU.
• The 14-bit control word when applied to the selection inputs specify a particular micro
operation.

For R1 ←R2 + R3, The Control word is

010 011 001 00010
 CONTROL
R1 R2 - R3
=
WORD Contd.
Input
Clock

R1 R2
R2
R3
R3
R4
R5
R6
R7
Load
(7 lines)
SELA { MUX MUX } SELB
010 011
3x8
A bus B bus
decoder

001 SELD
OPR ALU
00101

Output

Control word: 010 011 001 00101

CONTROL WORD Contd.
 STACK ORGANIZATION
• A useful feature that is included in the CPU of most computers is a stack or last-in,
first-out (LIFO) list.

• A stack is a storage device that stores information in such a manner that the item
stored last is the first item retrieved.
• The operation of a stack can be compared to a stack of trays. The last tray placed
on top of the stack is the first to be taken off.
• The stack in digital computers is essentially a memory unit. The register that holds
the address for the stack is called a stack pointer (SP) because its value always
points at the top item in the stack.

• The two operations of a stack are the insertion and deletion of items.

• The operation of insertion is called push. The operation of deletion is called Pop.
 STACK ORGANIZATION
Contd.
Types:
Register Stack: A stand alone unit that consists of collection of
finite number of registers / A stack can be placed in a portion of
a large memory or it can be organized as a collection of a finite
number of memory words or registers
Memory stack: This Stack can be implemented in RAM memory
attached to CPU. Only by assigning special part of it for stack
operations
 REGISTER STACK ORGANIZATION
• In a 64- word stack, the stack pointer contains 6 stack Address

bits (26 = 64). 63

Flags
• Since SP has only six bits, it cannot exceed a
FULL EMPTY
number greater than 63 (111111 in binary).
• The one-bit register FULL is set to 1 when the Full=0 Empty=1
stack is full
4
• EMPTY register is 1 when the stack is empty. SP=000010
3
SP=000001
• The data register DR holds the data to be written SP=000000 2
Data 2
into or read from the stack. Data 1 1

• Initially, SP is cleared to 0, EMTY is set to 1, and SP 0

FULL is cleared to 0, so that SP points to the Stack pointer DR

word at address 0 and the stack is marked empty

DATA 1
and not full. PUSH
DATA 2
• If the stack is not full (if FULL = 0), a new item is
inserted with a push operation.
 REGISTER STACK ORGANIZATION Contd.
Full =0 Empty=1
• Since SP has only six bits, it cannot exceed Full =1 Empty=0 stack Address

a number greater than 63 (111111 in SP=111111 63

binary).
• When 63 is incremented by 1, the result is 0
since 111111 + 1 = 1000000 in binary.
• SP can accommodate only the six least 4
significant bits C 3
The push operation is implemented with the following B 2
sequence of Micro operations; A 1
DATA 0

SP <- SP + 1 //Increment stack pointer DR

M [SP] <- DR //Write item on top of the stack

If (SP = 0) then (FULL <--1) //Check if stack is full DATA
EMTY <--0 //Mark the stack not empty
PUSH
M[SP] denotes the memory word specified by the address
presently available in SP
 REGISTER STACK ORGANIZATION
Contd.
stack Address

• A new item is deleted from the stack if the stack is Flags 63

not empty (if EMTY = 0). FULL EMPTY

Stack pointer
4
SP C 3
The pop operation consists of the following sequence B 2
of micro operations: A 1
0

DR <--M [SP] //Read item from the top of stack DR

SP <--SP – 1 //Decrement stack pointer

If (SP = 0) then (EMTY <--1) //Check if stack is empty
FULL <--0 //Mark the stack not full
 MEMORY STACK ORGANIZATION Contd.
• The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer.
• A portion of computer memory partitioned into three segments: program, data, and stack.
• Program Counter(PC) points to next instruction to be executed.
• Address Register(AR) points to array of data of operands.
• Stack Pointer (SP) points to top of stack.

New item is inserted with Push operation,

then SP is decremented.
SP ← SP-1
M [SP] ← DR

SP is incremented, then Last item is removed

with Pop operation,
DR ← M [SP]
SP ← SP +1

As shown in figure initial value of SP is 4001 and first item when

pushed in
 REVERSE POLISH NOTATION (RPN)
• A stack organization is very effective for evaluating arithmetic expressions
• The common arithmetic expressions are written in infix notation, with each
operator written between the operands.
• Consider the simple arithmetic expression
• To evaluate this arithmetic expression it is necessary to compute the product A •
B, store this product while computing C • D, and then sum the two products
• To evaluate arithmetic expressions in infix notation it is necessary to scan back
and forth along the expression to determine the next operation to be performed.
• The Polish mathematician Lukasiewicz showed that arithmetic expressions can be
represented in prefix notation . This representation, often referred to as Polish
notation, places the operator before the operands. The postfix notation, referred to
as reverse Polish notation (RPN), places the operator after the operands.
 REVERSE POLISH NOTATION (RPN)
Contd.
The 3 notations to evaluate expressions
1. A + B Infix notation
2. +AB Prefix notation (Polish notation)
3. AB+ Postfix notation (Reverse Polish Notation)

Expression A*B + C*D is written in RPN as AB*CD*+. And will

computed as
(A*B) CD *+
(A*B)(C*D)+
• Scan the expression from left to right.
• When an operator is reached, perform the operation with the two operands found on the left
side of the operator.
• Remove the two operands and the operator and replace them by the number obtained from
the result of the operation.
• Continue to scan the expression and repeat the procedure for every operator encountered
until there are no more operators.
 REVERSE POLISH NOTATION (RPN)
Contd.
• Reverse polish notation combined with stack comprised of registers is
most efficient way to evaluate expression.
• Stacks are good for handling long and complex problems involving chain
calculations.
• But need first to convert arithmetic expressions into parenthesis-free
reverse polish notation.
Example

Convert (3*4) +(5*6) to Reverse Polish Notation

 STACK OPERATIONS TO
EVALUATE ARITHMETIC EXPRESSION

6
4 5 5 30
3 3 12 12 12 12 42

3 4 * 5 6 * +
 BASIC COMPUTER ORGANIZATION

• Computer Registers
• Computer Instructions
• Timing and Control
• Instruction Cycle
 NEED OF REGISTERS
• Computer instructions are normally stored in consecutive memory locations
and are executed sequentially one at a time.
• The control reads an instruction from a specific address in memory and
executes it. It then continues by reading the next instruction in sequence
and executes it, and so on.
• This type of instruction sequencing needs a counter to calculate the
address of the next instruction after execution of the current instruction is
completed.
• It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory.
• The computer needs processor registers for manipulating data and a
register for holding a memory address.
 THE BASIC COMPUTER

The Basic Computer has two components, a processor and RAM

CPU
memory 0

• The memory unit has a capacity of 4096 words and each

word contains 16 bits.
15 0
• Twelve bits of an instruction word are needed to specify
the address of an operand.
• This leaves three bits for the operation part of the
4095
instruction and a bit to specify a direct or indirect address
– 4096 = 212, so it takes 12 bits to select a word in
memory

• Each word is 16 bits long

THE BASIC COMPUTER REGISTERS
 PROCESSOR REGISTERS
• A processor has many registers to hold instructions, addresses, data, etc

• The processor has a register, the Program Counter (PC) that holds the memory
address of the next instruction to be executed

– Since the memory in the Basic Computer only has 4096 locations, the PC only needs
12 bits

• In a direct or indirect addressing, the processor needs to keep track of what locations
in memory it is addressing: The Address Register (AR) is used for this - The AR is a
12 bit register in the Basic Computer

• When an operand is found, using either direct or indirect addressing, it is placed in the
Data Register (DR). The processor then uses this value as data for its operation

• The Basic Computer has a single general purpose register – the Accumulator (AC)
 PROCESSOR REGISTERS Contd.

• The significance of a general purpose register is that it can be referred to in

instructions
e.g. load AC with the contents of a specific memory location; store the contents
of AC into a specified memory location
• Often a processor will need a scratch register to store intermediate results or
other temporary data; in the Basic Computer this is the Temporary Register (TR)
• The Basic Computer uses a very simple model of input/output (I/O) operations
– Input devices are considered to send 8 bits of character data to the processor
– The processor can send 8 bits of character data to output devices
• The Input Register (INPR) holds an 8 bit character gotten from an input device
• The Output Register (OUTR) holds an 8 bit character to be send to an output
device
 COMMON BUS SYSTEM

• The basic computer has eight registers, a memory unit, and a control unit.
Paths must be provided to transfer information from one register to another and
between memory and registers.
• The number of wires will be excessive if connections are made between the
outputs of each register and the inputs of the other registers.
• A more efficient scheme for transferring information in a system with many
registers is to use a common bus.
• The outputs of seven registers and memory are connected to the common
bus.
• The specific output that is selected for the bus lines at any given time is
determined from the binary value of the selection variables S2, S1, and S0.
• The number along each output shows the decimal equivalent of the required
binary selection.
COMMON BUS SYSTEM Contd.
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
• Three control lines, S2,
PC 2 S1, and S0 control
LD INR CLR which register the bus
DR 3
selects as its input
LD INR CLR
S2 S1 S0 Register
E
ALU AC 4 0 0 0 x
LD INR CLR 0 0 1 AR
0 1 0 PC
INPR 0 1 1 DR
1 0 0 AC
IR 5
1 0 1 IR
LD 1 1 0 TR
TR 6
1 1 1 Memory
LD INR CLR
OUTR
Clock
LD
16-bit common bus
 COMMON BUS SYSTEM Contd.
• Either one of the registers will have its load signal activated, or the memory will have its
read signal activated
– Will determine where the data from the bus gets loaded
 Four registers, DR , AC, IR, and TR, have 16 bits each. Two registers, AR and PC, have
1 2 bits each since they hold a memory address.
 When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to O's. When AR or PC receive information from the bus, only the 12
least significant bits are transferred into the register.
 The input register INPR and the output register OUTR have 8 bits each and communicate
with the eight least significant bits in the bus.
 INPR is connected to provide information to the bus but OUTR can only receive
information from the bus.
 This is because INPR receives a character from an input device which is then transferred
to AC .
 OUTR receives a character from AC and delivers it to an output device. There is no
transfer from OUTR to any of the other registers.
 COMMON BUS SYSTEM Contd.
• The input data and output data of the memory are connected to the common bus, but the
memory address is connected to AR
• Therefore, AR must always be used to specify a memory address. By using a single
register for the address, we eliminate the need for an address bus that would have been
needed otherwise
• The content of any register can be specified for the memory data input during a write
operation. Similarly, any register can receive the data from memory after a read operation
except AC
• The 16 inputs of AC come from an adder and logic circuit. This circuit has three sets of
inputs. One set of 16-bit inputs come from the outputs of AC .
• They are used to implement register microoperations such as complement AC and shift
AC . Another set of 16-bit inputs come from the data register DR .
• The inputs from DR and AC are used for arithmetic and logic microoperations, such as
add DR to AC or AND DR to AC .
• The result of an addition is transferred to AC and the end carry-out of the addition is
transferred to flip-flop E extended AC bit). A third set of 8-bit inputs come from the input
register INPR
 INSTRUCTIONS
• Program

• A sequence of (machine) instructions

• (Machine) Instruction

A group of bits that tell the computer to perform a specific

operation (a sequence of micro-operation)

• The instructions of a program, along with any needed data are stored
in memory

• The CPU reads the next instruction from memory, It is placed in an

Instruction Register (IR)

• Control circuitry in control unit then translates the instruction into the
sequence of microoperations necessary to implement it
 INSTRUCTION FORMAT
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for that instruction
– An address that specifies the registers and/or locations in memory to use for that
operation
• In the Basic Computer, since the memory contains 4096 (= 212) words, we needs 12 bit
to specify which memory address this instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0: direct
addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits long, that leaves 3
bits for the instruction’s opcode

15 12 11 0
I
14 Opcode Address
Instruction Format
Addressing
mode
DIRECT AND INDIRECT ADDRESSING
 BASIC COMPUTER INSTRUCTIONS

I=0, Direct addressing mode

• Basic Computer Instruction Format
I=1, Indirect addressing mode

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 0
1 1 1 1 I/O operation
12 11
 BASIC COMPUTER INSTRUCTIONS Contd.

I=0, Direct addressing mode

0 000 ---- ---- ---- 0XXX

0 001 ---- ---- ---- 1XXX

1 X X X
0 110 ---- ---- ---- 6XXX

I=1, InDirect addressing mode

1 000 ---- ---- ---- 8XXX

1 001 ---- ---- ---- 9XXX

1 110 ---- ---- ---- EXXX

 BASIC COMPUTER INSTRUCTIONS Contd.

7
0 111 ---- ---- ---- 7XXX

7 X X X
 BASIC COMPUTER INSTRUCTIONS Contd.

F
1 111 ---- ---- ---- FXXX

X X X
F
BASIC COMPUTER INSTRUCTIONS Contd.
Symbol Hex Code Description
I=0 I=1
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA STA 2xxx Axxx Load AC from memory
BUN 3xxx Bxxx Store content of AC into memory
BSA 4xxx Cxxx Branch unconditionally
ISZ 5xxx Dxxx Branch and save return address
6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
FETCH , DECODE AND EXECUTE CYCLE VIDEO

https://www.youtube.com/watch?v=XM4lGflQFvA
 INSTRUCTION CYCLE
• In Basic Computer, a machine instruction is executed in the following cycle:
• Fetch an instruction from memory
• Decode the instruction

• Read the effective address from memory if the instruction has an indirect
address

• Execute the instruction

• After an instruction is executed, the cycle starts again at step 1, for the next
instruction
Note: Every different processor has its own (different) instruction cycle
EXAMPLE INSTRUCTION
PROCESSOR ARCHITECTURE
FETCHING AN INSTRUCTION
FETCHING AN INSTRUCTION Contd.
FETCHING AN INSTRUCTION Contd.
FETCHING AN INSTRUCTION Contd.
FETCHING AN INSTRUCTION Contd.
FETCHING AN INSTRUCTION Contd.
 FETCH and DECODE
T0: AR  PC (S0S1S2=010, T0=1)

• Fetch and Decode T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)

0 T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

1
T1 0
1 S2
1 1
T0 Bus
1 S1
0
1 S0
Memory
unit
7
111 IR
Address
Read

AR 1

LD I  IR(15)
PC 2 010 D0, . . . , D7  Decode IR(12-14)

IR (14-12) D7 D6 D5 D4 D3 D2 D1 D0
INR 0 0 0 0 0 0 0 0 0 0 1

IR 5 0 0 1 0 0 0 0 0 0 1 0

LD 0 1 0 0 0 0 0 0 1 0 0
Clock
Common bus
AR  IR(0-11)
 BASIC COMPUTER INSTRUCTIONS

I=0, Direct addressing mode

• Basic Computer Instruction Format
I=1, Indirect addressing mode

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 0
1 1 1 1 I/O operation
12 11
 DETERMINE THE TYPE OF INSTRUCTION
Start
SC  
Flow chart for Instruction Cycle
AR  PC
IR (14-12) D7 D6 D5 D4 D3 D2 D1 D0
T1 0 0 0 0 0 0 0 0 0 0 1
IR  M[AR], PC  PC + 1
0 0 1 0 0 0 0 0 0 1 0
T2
Decode Opcode in IR(12-14), 1 1 1 1 0 0 0 0 0 0 0
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0
Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR  M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.
 MICROOPERATIONS
Microoperations are classified into four categories:
 
– Register transfer microoperations (data moves from register
to register)
 
– Arithmetic microoperations (perform arithmetic on data in
registers)
 
– Logic microoperations (perform bit manipulation on data in
registers)
 
– Shift microoperations (perform shift on data in registers)
 ARITHMETIC MICROOPERATIONS

• Unlike register transfer microoperations, arithmetic microoperations change the information

content.
• The basic arithmetic microoperations are:
– addition
– subtraction
– increment
– decrement
Multiplication and division are not considered microoperations.
– Multiplication is implemented by a sequence of adds and shifts.
– Division is implemented by a sequence of subtracts and shifts.

 
ARITHMETIC MICROOPERATIONS Contd.
 BINARY ADDER

• To implement the add microoperation with hardware we need the

registers to hold the data and a digital circuit to perform the
addition (called a binary adder)
• The binary adders is constructed using full adders connected in
cascade so that the carry produced by one full adder becomes an
input for the next
•  Adding two n-bit numbers requires n full adders
• The n data bits for A and B might come from R1 and R2
respectively
 BINARY ADDER Contd.
A= A3 A2 A1 A0
To add two 4 bit numbers A and B, four full B = B3 B2 B 1 B 0
adders are required S = S 3 S2 S 1 S0

Truth table of Full Adder

A B Sum Carry C
S

A Full Sum (S) 0 0 0 0

Adder 0 1 1 0
B (FA) Carry (C )
1 0 1 0

1 1 0 1
ADDER-SUBTRACTOR
 ADDER-SUBTRACTOR Contd.
0 1 1

=1
0
1 1

1
0

M= 0 , Indicates addition
A-B→A+B’+1 M= 1 , Indicates Subtraction
A= A3 A2 A1 A0
• In an ExOR gate, if any one of the inputs is 0, Output = Input B = B’3 B’2 B’1 B’0
• If one of the inputs is 1, Output = Input’ 1
S = S 3 S2 S 1 S0
BINARY INCREMENTER
ARITHMETIC CIRCUIT
 4 BIT ARITHMETIC CIRCUIT
0
0
0 A0 0

0 A0+B0+0 =A0+B0
B0 0 B0

A1+B1
0
0

A2+B2
0
0

A3+B3
0
0

D= A + B (Add micro operation)

ARITHMETIC CIRCUIT FUNCTION
TABLE
LOGICAL MICROOPERATIONS
TRUTH TABLE FOR 16 2-VARIABLE
FUNCTION
SIXTEEN LOGICAL MICROOPERATIONS
SIXTEEN LOGICAL MICROOPERATIONS Contd.
ONE STAGE OF A LOGIC CIRCUIT
SHIFT MICROOPERATIONS
SHIFT MICROOPERATIONS
Contd.
 ARITHMETIC SHIFT RIGHT
• Arithmetic Shift Right, leaves sign bit unchanged
• Sign bit is 0 for positive and 1 for negative

Arithmetic Shift Right

n-2
4-BIT COMBINATIONAL CIRCUIT
SHIFTER
ARITHMETIC LOGIC SHIFT
UNIT
FUNCTIONAL TABLE FOR ARITHMETIC
LOGICAL SHIFT UNIT