William Stallings

Computer Organization
and Architecture
8th Edition

Internal Memory
Computer Memory Overview
The memory is that part of computer where programs and
data are stored. The basical concept is the following:
• Bits
— The basic unit of memory is the binary digit called a bit. A bit
may contain a 0 or 1. It is the simplest possible unit
• Memory addresses
— Memories consist of a number of cells or locations each of
which can store a piece of information. Each location has a
number called its address, by which program can refer to it.
The cells is the smallest addressable
— Byte: 8-bits
— Bytes are grouped into words. The significance of word is that
most instruction operate on entire word. A computer with a
32bit/word has 4 bytes/word
• Byte ordering
— The bytes in a word can be numbered from left-to-right or
right-to-left.
— The former system, where the numbering begin at the “big”
(i.e, high-order) end is called a big endian computer, such as
the SPARC or the big IBM mainframes. In contras it is a little
endian computer, such as the Intel family using right-to-left
numbering for the representation of a 32 bit computer.
 Key Characteristics of Computer Memory
Systems
• Location • Performance
— Processor — Access time
— Internal (main) — Cycle time
— External (secondary) — Transfer rate
• Capacity • Physical Type
— Word size — Semiconductor
— Number of words — Magnetic
• Unit of Transfer — Optical
— Word — Magneto-Optical
— Block • Physical Characteristics
• Access Method — Volatile/nonvolatile
— Erasable/nonerasable
— Sequential
— Direct • Organization
— Random
— Associative
Characteristics of Computer Memory
• Capacity: the amount of information that can be contained in a
memory unit -- usually in terms of words or bytes
• Memory word: the natural unit of organization in the memory,
typically the number of bits used to represent a number
• Addressable unit: the fundamental data element size that can be
addressed in the memory -- typically either the word size or
individual bytes
• Unit of transfer: The number of data elements transferred at a
time – usually bits in main memory and blocks in secondary
memory
• Transfer rate: Rate at which data is transferred to/from the
memory device
• Access time:
— For RAM, the time to address the unit and perform the transfer
— For non-random access memory, the time to position the R/W head
over the desired location
• Memory cycle time: Access time plus any other time required
before a second access can be started
• Access technique: how are memory contents accessed
Memory Access Methods
• Random access:
— Each location has a unique physical address
— Locations can be accessed in any order and all access times are the same
— What we term “RAM” is more rightly called read/write memory since this access
technique also applies to ROMs as well
— Example: main memory
• Sequential access:
— Data does not have a unique address
— Must read all data items in sequence until the desired item is found
— Access times are highly variable
— Example: tape drive units
• Direct access:
— Data items have unique addresses
— Access is done using a combination of moving to a general memory “area”
followed by a sequential access to reach the desired data item
— Example: disk drives
• Associative access:
— A variation of random access memory
— Data items are accessed based on their contents rather than their actual location
— Search all data items in parallel for a match to a given search pattern
— All memory locations searched in parallel without regard to the size of the memory
— Extremely fast for large memory sizes
— Cost per bit is 5-10 times that of a “normal” RAM cell
— Example: some cache memory units.
Types of Memory
Computer memory system consists a various types of memory. Manufactures
produce a number of different types of memory devices having a variety
of technologies. The technology affect not only the operating chracteristics
but also the manufacturing cost. In the section following we present an
overviews of types of memory.

• Main Memory (“Internal” memory components)

— RAM (read-write memory): Static RAM, Dynamic RAM
— ROM (Read Only Memories) : ROMs, PROMs, EPROMs,
EEPROMs, Flash Memory.
• Cache memory
— The cache memories are high-speed buffers for holding recently
accessed data and neighboring data in main memory. The organization
and operations of cache provide an apparently fast memory system.
• External Memory
— Magnetic disks
— RAID technology disks
— Optical disks
— Magnetic tape
 Semiconductor Memory Types
Memory Type Category Erasure Write Mechanism Volatility

Random-access
Read-write memory Electrically, byte-level Electrically Volatile
memory (RAM)

Read-only
Masks
memory (ROM)
Read-only memory Not possible

Programmable
ROM (PROM)

Erasable PROM
UV light, chip-level
(EPROM) Nonvolatile

Electrically

Electrically Erasable Read-mostly memory

Electrically, byte-level
PROM (EEPROM)

Flash memory Electrically, block-level

Semiconductor.....
• The use of semiconductor for main
memory is almost universal.
• The basic elements of semiconductor
memory is memory cells.
• All semiconductor cells shares the
following properties:
—They exhibits two stable (semi stable)state
which can be represent binary 1or 0.
—Capable of written to the state
—Capable of read to sense the state
Memory Cell Operation
Semiconductor......
• As shown above the cells has three
functional terminal capable of carrying an
electric signal:
—Select terminal : select memory for read or
write operation
—Control terminal : indicates the read or write
Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is
random access
—both read /write is accomplished by electric
signal
—Volatile
—Temporary storage
—Static or dynamic
Dynamic RAM
• Is made with the cell that store data as a charge
on capacitor
• The presence and absence of a charge are
indicated by binary 1or 0.
• Need refreshing even when powered to maintain
data storage
• Simpler construction
• Less expensive
Dynamic.......
• Need refresh circuits
• Slower
• Main memory
Dynamic RAM Structure
DRAM Operation
• Address line active when bit read or written
— Transistor switch closed (allowing current to flows)
— Transistor is closed if a voltage is applied to address
line and open if no voltage is present on the address
line.
• Write
— Voltage signal is applied to bit line
– High for 1 low for 0
— A signal is applied to the address line
— Then signal address line
– allowing charge to be transferred to the capacitor
DRAM........
• Read
— Address line selected
– transistor turns on and the charge stored
— Charge from capacitor fed via bit line to sense amplifier
– Compares with reference value to determine 0 or 1
— Capacitor charge must be restored to complete
operation
Static RAM
• Is using the same logical elements used in
processor
• Bits stored as on/off switches
• No refreshing needed when powered
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache

—Uses flip-flops
Stating RAM Structure
Static RAM Operation
• Transistor arrangement gives stable logic
state
• State 1
—C1 high, C2 low
—T1 T4 off, T2 T3 on
• State 0
—C2 high, C1 low
—T2 T3 off, T1 T4 on
• Address line transistors T5 T6 is switch
• Write – apply value to B & compliment to
B
• Read – value is on line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller cell
—More dense(more cell per area)
—Less expensive
—Needs refresh
— favoured for Larger memory units
• Static
—Faster
—Cache
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• It is possible to read from ROM but not
write new data
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
• Advantage
—The data or program is permanently in main
memory and need never be loaded from
secondary storage devices
Types of ROM
• Written during manufacture
—Very expensive for small runs
• Programmable (once)
—PROM
—Needs special equipment to program
• Read “mostly”
—Erasable Programmable (EPROM)
– Erased by UV
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
Types .......
• Flash memory
—Is intermediate in cost and functionalities b/n
EPROM and EEPROM
—It use an electrical erasing technology
—Much faster than EPROM
– Erase whole memory electrically
Organisation in detail
• For semiconductor memory one of the key
designing issue is the no of bit of data
that may be read/write at a time
• A 16Mbit chip can be organised as 1M of
16 bit words
• A bit per chip system has one bit per chip
organization which means that data is
read/written one bit at a time.
Organization......
• Example : let us see a typical organization
of a 16MB DRAM
• In this case 4bits are read/write at a time.
• The memory array is organized as four
square array of 2048 by 2048
• The elements of the array are connected
by both horizontal and vertical line.
• Each horizontal line connected to the
selected terminal of each cell in its raw
• Each vertical line connected to the data in/
sense terminal of each cell in the column
—Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4
capacity
Refreshing
• Refresh circuit included on chip
• Disable DRAM chip when all data cell are
refreshed on the chip
• Counter step through all rows value
• Read & Write back from the same location
and this allow for the cell to refresh
• Takes time and resulted in Slows down
apparent performance
Typical 16 Mb DRAM (4M x 4)
• 11 address line selects one of the 2048
column of 4bit per column
• Four data line are used for input and
output of 4bit to and from a data buffer
• b/c only 4 bit are read/write to this DRAM
there must be multiple DRAM connected
to the memory controller to read/write
word data to the bus
Packaging
• in the above example in 8mb organization as
1m*8 in which organization treated as one word
per chip package
• The package includes 32 pin to interconnect to
the outside world
• Pins include:
—Address of the word being accessed(A0-A19)
—The data to be read out(D0-D7)
—The power supply to the chip(Vcc)
—A ground pin(Vss)
—A chip enable(CE)
—A program voltage(Vpp)(write operation)
Interleaved Memory
• Collection of DRAM chips
• Grouped into memory bank
• Banks independently service read or write
requests
• K banks can service k requests
simultaneously
Error Correction
• Hard Failure
—Permanent defect so that the memory cell
affected and can not store data
—This error can be caused may be by harsh
environmental abuse , manufacturing error..
• Soft Error
—Random, non-destructive events that alter one
or more memory cell contents with out
damaging the memory
—No permanent damage to memory
—Caused most of the time by power supply
error
• Detected using Hamming error correcting code
Error Correcting Code Function
Advanced DRAM Organization
• Basic DRAM same since first RAM chips
• Enhanced DRAM
—Contains small SRAM as well
—SRAM holds last line read (c.f. Cache!)
• Cache DRAM
—Larger SRAM component
—Use as cache or serial buffer
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional DRAM)
• Since SDRAM moves data in time with system
clock, CPU knows when data will be ready
• CPU does not have to wait, it can do something
else
• Burst mode allows SDRAM to set up stream of
data and fire it out in block
• In burst mode a series of data can be clocked out
rapidly after the first bit accessed
• Useful when the bit accessed are in sequence and
in the same raw of the array
SDRAM...
• Advantage:
—Has multiple bank internal architecture that
improve opportunity on the chip parallelism
—Mode register and associated control logic
—The mode register specify the burst length
which means that the number of separate
unites of data synchronously fed on to bus
—Performs best when it is transfer large blocks
of data
SDRAM
SDRAM Read Timing
RAMBUS
• Adopted by Intel for Pentium & Itanium
• Main competitor to SDRAM
• Vertical package – all pins on one side
• Data exchange over 28 wires < cm long
• Bus addresses up to 320 RDRAM chips at
1.6Gbps
• Asynchronous block protocol
—480ns access time
—Then 1.6 Gbps
RAMBUS Diagram
DDR SDRAM
• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data
twice per clock cycle
—Rising edge and falling edge
DDR SDRAM
Read Timing
Simplified DRAM Read Timing
Cache DRAM
• Mitsubishi
• Integrates small SRAM cache (16 kb) onto
generic DRAM chip
• Used as true cache
—64-bit lines
—Effective for ordinary random access
• To support serial access of block of data
—E.g. refresh bit-mapped screen
– CDRAM can prefetch data from DRAM into SRAM
buffer
– Subsequent accesses solely to SRAM
Reading
• The RAM Guide
• RDRAM