Assembly Language

Programming Languages Generations:

1.Machine Language: This is the machine
code language a computer works with. It
consists of a series of binary numbers
which a computer interprets as instructions
or data. Very difficult for human beings to
program in this language.
 Assembly Language..
2. Assembly Language: This consists of
abbreviations closer to human language
(English). Each abbreviation stands for
exactly one machine code instruction. As
such there is a 1 to 1 relationship between
assembly language instruction and the
machine code instruction. There is no
standard. Each CPU has its own assembly
language. CPUs from one family share
many assembly language instructions.
 Assembly Language..
3. High Level Language: This consists of
Statements much closer to the human
language (English). A single statement can
represent several or tens of machine code
instructions. It is non-machine specific.
The same source program can be compiled
for different machine types. A statement
like Writeln or printf requires a series of
machine code instructions to perform the
requied display.
 Assembly Language..
4. 4GL Language: This is the 4th generation
programming language. Consists of
Statements that tell the computer WHAT
to do but not HOW to do the required task.
For example to sort an array to ascending
or descending order one must write nested
loops in a high level language to
accomplish the task. With 4GL a computer
is requested to sort by Ascending or
Descending order without specifying how
the sorting should be accomplished.
 Assembly Language..
The machine language and assembly
language belong to what is known as Low
Level programing languages.

High level and 4GL languages belong to

what is known as High Level
programming languages
 Assembly Language..
As mentioned earlier computers only work
in machine language. As such source
programs not written in machine language
have somehow got to be converted
(translated) into machine language for them
to be executed by a CPU. This process gave
rise to the following terminologies:
 Assembly Language..
1. Compiler: An application program that
converts a source program written in a
high level programming language into
machine code. The generated machine
code can be placed in memory for
execution and can also be saved as an
executable file i.e. *.EXE. Basically a
Compiler converts the entire source
program (before execution). The presence
of Syntax errors causes the abortion of the
compilation process.
 Assembly Language..
2. Assembler: An application program
that Assembles (Converts) a source
program written in Assembly
programming language into machine
code. The assembling process does not
entertain Syntax errors. A program
must first be syntax error free for it to
be assembled.
 Assembly Language..
2. Interpreter: An application program that
interprets (Converts) a source program
written in high level programming
language into machine code. The
interpretation is done statement by
statement i.e. 1st statement is converted to
machine code and executed. This process
is repeated for subsequent statements.
 Assembly Language..
The interpreter does not save converted machine
code. Programs executed through an interpreter are
normally slow as the conversion process consumes
most of the time. Program execution can start even
if there are syntax errors. It will only terminate
when the 1st syntax error is encountered. Over time
interpreters have been improved to generate
machine code first. Examples of such interpreter
languages are BASIC (some dialects) ,PHP,
JavaScript, and Python. Enables them to be Cross-
platform.
 Intel 8085 Instructions Set
The Intel 8085 instructions are divided into 5
groups:
1.Data Transfer Group
2.Arithmetic Group
3.Logic Group
4.Branch Group
5.Stack, I/O and Machine Control Group
 Intel 8085 Instructions Set..
As an introduction to Intel 8085
Assembly language we shall go
through all the instructions for the
first 3 groups. The instructions in
the remaining 2 groups will come
along as we go through the Course.
 Data Transfer Group Instructions
Instructions in this group handle data transfer between
CPU registers and between CPU and Memory. The
convention used by Intel is the data destination is
specified first while the data source is specified last.

The Symbol <x> is used to refer to the content of x

which can be a register, register pair, or Memory
address.

All MOVE instruction are COPY instructions with the

data source left unaffected. However the destination is
overwritten.
 1. MOV r1, r2 (Move Register)
The content of 8-bit Register r2 is copied to another
8-bit register r1.
Example: Suppose Register B contains 50H
i.e..<B> = 50H
Executing:
MOV A, B
Causes <A> = <B> = 50H
Content of register B copied to Register A
This instruction alone covers more than 40
actual instructions i.e. combination of r1 and r2.
 2. MOV r, M (Move from Memory)
The content of memory location whose address is
in Register pair H is copied to 8-bit register r

Example: Suppose Register pair H contains (points

to) memory address 2060H that happens to contain
77H i.e. <HL> = 2060H and <2060H> = 77H
Executing:
MOV B, M
Causes <B> = <2060H> = 77H
Content of Memory copied to Register B
3. MOV M, r (Move to Memory)
The content of specified 8 bit register r is copied to
memory location whose address is in Register pair
H.

Example: Suppose Register C contains 33H and

Register pair H contains (points to) memory
address 2040H i.e. <C> = 33H, and <HL> = 2040H
Executing:
MOV M,C
Causes <2040H> = <C> = 33H
Content of Register C copied to Memory
 4. MVI r, data8 (Move Immediate)

The specified 8 bit data is copied to the

specified 8-bit Register r.

Executing:
MVI A,60H
Causes <A> = 60H
Instruction is used to initialise (set) an 8-
bit register to a desired value.
 5. MVI M, data8
(Move to Memory Immediate)
The specified 8 bit data is copied to the
memory location whose address is in
Register pair H..
Example: Let <HL> = 2860H
Executing:
MVI M,20H
Causes <2860H> = 20H
Instruction is used to initialise (set) a
memory location to a desired value.
 6. LXI rp, data16
(Load Register Pair Immediate)
The specified register pair rp, is loaded with
the specified 16-bit address or data.
Executing:
LXI H, 2060H
Causes <HL> = 2060H
Instruction is used to initialise (set) a
register pair to a desired 16 bit
address/data
 7. LDA address
(Load Accumulator Direct)
The content of the specified memory address
is copied to the Accumulator (Register A)
Example: Assume memory address location
2050H contains 88H i.e. <2050H> = 88H
Executing:
LDA 2050H
Causes <A> = <2050H > = 88H
 8. STA address
(Store Accumulator Direct)
The content of the Accumulator is Copied
(stored) to the specified memory address.
Example: Assume the Accumulator contains
22H i.e. <A> = 22H
Executing:
STA 2055H
Causes <2055H > = <A> = 22H
 9. LHLD address
(Load H and L Direct)
The contents of 2 memory locations starting at the specified
address are copied to register pair H in this manner:
<L> = <address>
<H> = <<address + 1>
Example: Assume memory locations 2080H and 2081H contain
10H and 15H respectively.
Executing:
LHLD 2080H

Causes <HL> = 1510H with <L> = <2080H> =

10H and <H> = <2081H> = 15H
 10. SHLD address
(Store H and L Direct)
The contents of register pair H is copied to 2 memory
locations starting at the specified address in this manner:
<address> = <L>
<<address + 1> = <H>
Example: Assume register pair H contains 3080H
Executing:
SHLD 2070H

Causes <2070H> = <L> = 80H and

<2071H> = <H> = 30H
 11. LDAX rp
(Load Accumulator Indirect)
The content of memory location whose address is in the
specified register pair is copied to the Accumulator
Example: Assume register pair B contains memory
address 2030H whose content is 99H.
Executing:
LDAX B

Causes <A> = <2030H> = 99H

Instruction allows register pair B and D to be used as
pointers to memory.

Recall MOV A,M for register pair H.

 12. STAX rp
(Store Accumulator Indirect)
The content of the accumulator is copied to the memory location
whose address is in the specified register pair .
Example: Assume register pair D contains memory address
2040H and the Accumulator contains 7FH.
Executing:
STAX D

Causes <2040H> = <A> = 7FH

Instruction allows register pair B and D to be used as pointers to
memory.

Recall MOV M,A for register pair H.

 13. XCHG
(Exchange H and L with D and E
The contents of register pair H is exchanged with
contents of register pair D in this manner:
<H> <D>
<L> <E>
Example: Assume <HL> = 50C7H and <DE> =
3070H
Executing:
XCHG

Causes <HL> = 3070H and <DE> = 50C7H

 13. XCHG …
In the absence of XCHG instruction 6
instructions would have to be used to
perform the required exchange:
MOV A,H
MOV H,D
MOV D,A
MOV A,L
MOV L,E
MOV E,A
 Arithmetic Group Instructions
Instructions in this Group perform
arithmetic operations using the following
rules:
1.For all 8-bit arithmetic operations one
of the operand has to be in the
accumulator before the operation.
2.For all 8-bit arithmetic operations the
Result is Stored in the Accumulator.
 1. ADD r (Add Register)
The content of the specified 8-bit register is
added to the content of the Accumulator.
Result is stored in the Accumulator.
Example: Assume <A> = 30H and <B> =
40H
Executing:
ADD B
Causes <A> = <A’> + <B>
<A> = 30H + 40H = 70H
 2. ADD M (Add Memory)
The content of the memory location whose
address is in register pair H is added to the content
of the Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 20H and register pair H
contains memory address 2040H that happens to
contain 10H.
Executing:
ADD M
Causes <A> = <A’> + <2040H>
<A> = 20H + 10H = 30H
 3. ADI data8 (Add Immediate)
The specified 8-bit data is added to
the content of the Accumulator.
Result is stored in the Accumulator.
Example: Assume <A> = 50H
Executing:
ADI 40H
Causes <A> = <A’> + 40H
<A> = 50H + 40H = 90H
 4. ADC r
(Add Register with Carry)
The content of the specified 8-bit register plus the CY
flag status are added to the content of the
Accumulator. Result is stored in the Accumulator.
Example: Assume <A> = 70H and <B> = 20H and
<CY> = 1
Executing:
ADC B
Causes <A> = <A’> + <B> + <CY>
<A> = 70H + 20H + 1
= 91H
 5. ADC M
(Add Memory with Carry)
The content of the memory location whose
address is in register pair H plus the status of the
CY flag are added to the content of the
Accumulator. Result is stored in the Accumulator.
Example: Assume <A> = 50H and register pair H
contains memory address 2050H that happens to
contain 30H and <CY> = 1.
Executing:
ADC M
Causes <A> = <A’> + <2050H> + <CY>
<A> = 50H + 30H + 1 = 81H
 6. ACI data8
(Add Immediate with Carry)
The specified 8-bit data plus the status of the
CY flag are added to the content of the
Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 30H and <CY> = 0
Executing:
ACI 25H
Causes <A> = <A’> + 25H + <CY>
<A> = 30H + 25H + 0 = 55H
 7. SUB r (Subtract Register)
The content of the specified 8-bit register is
Subtracted from the content of the
Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 80H and <C> =
30H
Executing:
SUB C
Causes <A> = <A’> - <C>
<A> = 80H - 30H = 50H
 8. SUB M (Subtract Memory)
The content of the memory location whose
address is in register pair H is subtracted from the
content of the Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 60H and register pair H
contains memory address 2050H that happens to
contain 25H.
Executing:
SUB M
Causes <A> = <A’> - <2050H>
<A> = 60H - 25H = 3BH
9. SUI data8 (Subtract Immediate)
The specified 8-bit data is subtracted
from the content of the Accumulator.
Result is stored in the Accumulator.
Example: Assume <A> = 50H
Executing:
SUI 40H
Causes <A> = <A’> - 40H
<A> = 50H - 40H = 10H
 10. SBB r
(Subtract Register with Borrow)
The content of the specified 8-bit register together
with the CY flag status are subtracted from the
content of the Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 70H and <B> = 20H and
<CY> = 1
Executing:
SBB B
Causes <A> = <A’> - <B> - <CY>
<A> = 70H - 20H - 1
= 4FH
 11. SBB M
(Subtract Memory with Borrow)
The content of the memory location whose address is in
register pair H together with the status of the CY flag are
subtracted from the content of the Accumulator. Result is
stored in the Accumulator.
Example: Assume <A> = 50H and register pair H
contains memory address 2050H that happens to contain
30H and <CY> = 1.
Executing:
SBB M
Causes <A> = <A’> - <2050H> - <CY>
<A> = 50H - 30H - 1 = 1FH
 12. SBI data8
(Subtract Immediate with Borrow)
The specified 8-bit data together with the status
of the CY flag are subtracted from the content
of the Accumulator. Result is stored in the
Accumulator.
Example: Assume <A> = 30H and <CY> = 0
Executing:
SBI 10H
Causes <A> = <A’> - 10H - <CY>
<A> = 30H - 10H - 0 = 20H
 13. INR r (Increment Register)
The specified 8-bit register is
incremented by 1
Example: Assume <D> = 40H
Executing:
INR D
Causes <D> = <D’> + 1
<D> = 40H + 1
= 41H
14. INR M (Increment Memory)
The content of memory location whose address
is in register pair H is incremented 1
Example: Register pair H contains memory
address 2050H that happens to contain 30H .

Executing:
INR M
Causes <2050H> = <2050>’ + 1
<2050H> = 30H + 1
= 31H
15. DCR r (Decrement Register)
The specified 8-bit register is
decremented by 1
Example: Assume <A> = 30H
Executing:
DCR A
Causes <A> = <A’> - 1
<A> = 30H - 1
= 2FH
16. DCR M (Decrement Memory)
The content of memory location whose address
is in register pair H is decremented by 1.
Example: Register pair H contains memory
address 2030H that happens to contain 41H .

Executing:
DCR M
Causes <2030H> = <2030>’ - 1
<2030H> = 41H - 1
= 40H
 17. INX rp
(Increment Register Pair)
The content of the specified register pair is
incremented by 1.
Example: Assume <HL> = 20FFH
Executing:
INX H
Causes <HL> = <HL’> + 1
<HL> = 20FFH + 1
= 2100H
Although Intel 8085 CPU is an 8 bit CPU the INX
instruction is executed 16-bitwise taking care of the
overflow from the lower register.
 18. DCX rp
(Decrement Register Pair)
The content of the specified register pair is
decremented by 1.
Example: Assume <BC> = 3100H
Executing:
DCX B
Causes <BC> = <BC’> - 1
<BC> = 3100H - 1
= 30FFH
Although Intel 8085 CPU is an 8 bit CPU the DCX
instruction is executed 16-bitwise taking care of the
borrow into the lower register.
 19. DAD rp
(Double Add Register Pair)
The content of the specified register pair is added to the
content of register pair H. The result is stored in register
pair H.
Example: Assume <BC> = 3500H and <HL> = 4700H
Executing:
DAD B
Causes <HL> = <HL’> + <BC>
<HL> = 4700H + 3500H
= 7C00H
Note: Register pair H behaves like a 16 bit Accumulator for
this 16-bit arithmetic operation.
 20. DAA
(Decimal Adjust Accumulator)
The content of the Accumulator is
adjusted to BCD according to these rules:
1.A 6 is added to the Accumulator nibble
if a nibble is above 9.
2.A 6 is added to the lower nibble in case
the AC flag = 1 and also a 6 is added to
the upper nibble if the CY flag = 1.
Used for BCD arithmetic.
 20. DAA …
Example: Assume <A> = 3AH and
both <CY> and <AC> = 0

Executing:
DAA
Causes <A> = <A’> + 06H
= 3AH + 06H = 40H
 20. DAA …
Example: Assume <A> = 71H and
<CY> = 0 but <AC> = 1

Executing:
DAA
Causes <A> = <A’> + 06H
= 71H + 06H = 77H
 Exercise
1. Write a program to add two
numbers 40H and 50H and store
the Result at Address 8180H.
2. Write a program to add content of
memory location at 8160H to
content of memory location at
8170H and store the result at
address 8190H.
 Solutions to Problem 1
In Assembly language programming there is
no unique solution. It all depends on the logic
one comes up with when programming.

This is illustrated by the following possible

solutions to Problem 1 for adding numbers
40H and 50H
 Solution 1
MVI A,40H ; get 1st number
ADI 50H ;Add it to the 2nd number

STA 8180H ;Store the result

 Solution 2
MVI A,50H ; get one of the numbers

ADI 40H ;Add it to the other number

STA 8180H ;Store the result

 Solution 3
MVI A,40H ;get 1st number

MVI B,50H ;get the 2nd number (Possible to

;use other 8 bit registers)
ADD B ;Add the 2 numbers

STA 8180H ;Store the result

 Solution 4
MVI A,40H ;get 1st number

ADI 50H ;Add it to the 2nd number

LXI H, 8180H ;Point to the storage memory

;location
MOV M,A ;Store result at designated
;location
 Solution 5
LXI H, 8180H ;Point to the storage
;memory location
MVI A,40H ;get 1st number
ADI 50H ;Add it to the 2nd number
MOV M,A ;Store result at designated
;location
 Solution 6
LXI B, 8180H ;Point to the storage
;memory location
MVI A,40H ;get 1st number
ADI 50H ;Add it to the 2nd number
STAX B ;Store result at designated
;location
 Solution 7
LXI D, 8180H ;Point to the storage
;memory location
MVI A,40H ;get 1st number
ADI 50H ;Add it to the 2nd number
STAX D ;Store result at designated
;location