8279

Keyboard and
Display
Controller
The INTEL 8279 is specially developed for interfacing keyboard and display
devices to 8085/8086/8088 microprocessor based system. The important
features of 8279 are,

• Simultaneous keyboard and display operations.

• It is designed to interface and control keyboard and display

peripherals. It relives CPU from scanning keyboards, refreshing
displays, debouncing key closures, blanking display etc.

• it provides two 4 bit display output ports, hence two separate

banks of 8/16 digit numeric displays can be interfaced. Two 4 bit
ports can also be used together as a single 8 bit port. Hence a
single bank of 16 characters alphanumeric display can be
interfaced.
 IRQ SHIFT

CNTL/ STB Key board

Data bus
Pins
RL0- RL7

SL0 – SL3
RD*
WR*
CS* OUT B0- B3
A0 Display Pins
OUT A0 – A3
RESET
CLK BD*
VCC VSS
CPU interface
Pins
Pins of 8259 can be divided into

Keyboard input pins

Display output pins

Scan pins

CPU interface input pins

Interface Pins
Pins Functions
Cs* When low 8279 is selected
RD* When low , 8085 reads from 8279
WR* When low 8085 writes into 8279
A0 It is an active high input line used to select control / status register and
when low keyboard or display section is selected.
Reset When it is high 8085 resets 8279
DB0-DB7 These are 8 b it bi-directional tristate buffered data lines. All the data
and commands between 8085 and 8279 are transferred via these lines.
IRQ When it goes high 8279 interrupts 8085 to read data which has come
from keyboard.
CLK Its an input line generally connected to the system clock. Its used to
generate internal timings.
A0 RD* WR* Function
0 0 1 Keyboard section
0 1 0 Display section
1 0 1 Status register
1 1 0 Command or control register
 Keyboard Pins
Pins Functions
RL0 – RL 7 Return lines: these are active low lines. These lines are connected to
columns of matrix type keyboard, columns of sensor matrix, and data
input lines of ASCII strobed keyboard. They have internal pull-ups to
keep them high continuously. Hence key closures, sensor values and
ASCII coeds should be active low.

SHIFT It is a special key input line. In case of typewriter keyboard, the shift key
is connected to this line. The signal on this line is recognized in scanned
keyboard mode only. The status of this key is stored in FIFO RAM. But
the line is not scanned by 8279.

CNTL / STB Control / strobe:

it’s a special key / handshake input line. In scanned keyboard mode, it
functions as a control input line. This is normally connected to control
key of the type writer keyboard. It is ignored in sensor matrix mode.
The status of control; key is also stored in FIFO RAM.
In strobed input mode, this line acts as STB input line. The data or ASCII
key code is entered into the FIFO RAM at the rising edge of this signal.
Display Pins
Pins Functions
OUT A0- A3 and These are two, 4 bit output ports of the 16 x 8 bit display RAM. These
OUT B0 – B3 ports are individually programmable, 8279 outputs contents of selected
locations of display RAM on these lines. These lines are connected to
the segment input of 7 segment display. These ports can be used
together as an 8 bit port.
BD* Blank Display:
It is an active low display output line. It is used to blank the display. It is
connected to the blanking input of the display. It is activated by using
blank display command.
SCAN Pins
Pins Functions
SL0 – SL3 SCAN Lines:
These lines are used by the display, keyboard and sensor matrix. Scan
lines can be operated in either encoded or decoded mode.
In decoded mode, these lines are connected to rows of keyboard and
common cathode or common anode of seven segment display. Only
one line is activated ( low ) ate a time.
In encoded mode, these lines are used along with external decoder to
generate maximum 8 rows scans and 16 digit strobes. Therefore SL0 –
SL2 must be externally decoded to generate 8row scans. In this mode
the maximum size of the matrix keyboard or sensor matrix is 8 x8, while
maximum size of 7 segment display is 16 digit.
Block diagram of 8279: CPU Keyboard

Display
The four major sections of 8279 are keyboard, scan, display
and CPU interface.

Keyboard section

Display section

Scan section

CPU interface section

Keyboard section:
• The keyboard section consists of eight return lines RL0 - RL7
that can be used to form the columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The
keys are automatically debounced.
• The two operating modes of keyboard section are 2-key
lockout and N-key rollover.
• In the 2-key lockout mode, if two keys are pressed
simultaneously, only the first key is recognized.
• In the N-key rollover mode simultaneous keys are recognized
and their codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO (First In First
Out) RAM.
• The FIFO can store eight key codes in the scan keyboard mode. The
status of the shift key and control key are also stored along with key
code. The 8279 generate an interrupt signal when there is an entry in
FIFO. The format of key code entry in FIFO for scan keyboard mode is,

• In sensor matrix mode the condition (i.e., open/close status)

of 64 switches is stored in FIFO RAM. If the condition of any of
the switches changes then the 8279 asserts IRQ as high to
interrupt the processor.
 Display section
• The display section has eight output lines divided into two groups A0-A3

and B0-B3.

• The output lines can be used either as a single group of eight lines or as

two groups of four lines, in conjunction with the scan lines for a

multiplexed display.

• The output lines are connected to the anodes through driver transistor

in case of common cathode 7-segment LEDs.

• The cathodes are connected to scan lines through driver transistors.

• The display can be blanked by BD (low) line.

• The display section consists of 16 x 8 display RAM. The CPU can read

from or write into any location of the display RAM.

Scan section:
• The scan section has a scan counter and four scan lines, SL0 to SL3.

• In decoded scan mode, the output of scan lines will be similar to a 2-

to-4 decoder.

• In encoded scan mode, the output of scan lines will be binary count,

and so an external decoder should be used to convert the binary

count to decoded output.

• The scan lines are common for keyboard and display.

• The scan lines are used to form the rows of a matrix keyboard and

also connected to digit drivers of a multiplexed display, to turn

ON/OFF.
CPU interface section
• The CPU interface section takes care of data transfer between 8279 and
the processor.
• This section has eight bidirectional data lines DB0 to DB7 for data
transfer between 8279 and CPU.
• It requires two internal address A =0 for selecting data buffer and A = 1
for selecting control register of8279.
• The control signals WR (low), RD (low), CS (low) and A0 are used for
read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven data transfer
with processor.
• The 8279 require an internal clock frequency of 100 kHz. This can be
obtained by dividing the input clock by an internal pre scaler.
• The RESET signal sets the 8279 in 16-character display with two -key
lockout keyboard modes.
Programming the 8279:
•The 8279 can be programmed to perform various functions through eight
command words.

Keyboard/Display Mode Set

 Program Clock

All timing and multiplexing signals for the 8279 are generated by an internal
prescaler. This prescaler divides the external clock (pin 3) by a programmable integer.
Bits PPPPP determine the value of this integer ranges from 2 to 31.

Example:
Choosing a divisor that yields 100 kHz will give the specified scan and debounce
times. For instance, if Pin 3 of the 8279 is being clocked by a 2 MHz signal, PPPPP
should be set to 10100 to divide the clock by 20 to yield the proper 100 kHz
operating frequency.

Example:
When the control word set to 2Ch (00101100b), the program clock command is
enabled (001) and the prescaler value = 12 (01100b).
At the result, the internal clock of the 8279 is equal to
( 2.4576 MHz /12=204.8 KHz).

In general Prescalar value = (external Clock / 100 KHz) ; for proper operation.
Read FIFO/Sensor RAM

0= fixed address mode.

x x x = in scan keyboard mode.
1= auto increment mode
A A A = address of sensor RAM

The CPU sets the 8279 for a read of the FIFO/Sensor RAM by first writing this
command. In the Scan Keyboard Mode, the Auto-Increment flag (AI) and the RAM
address bits (AAA) are irrelevant.

The 8279 will automatically drive the data bus for each subsequent read (A0=0) in the
same sequence in which the data first entered the FIFO.
All subsequent reads will be from the FIFO until another command is issued.

In the Sensor Matrix Mode, the RAM address bits AAA select one of the 8 rows of the
Sensor RAM.

If the AI flag is set (AI=1), each successive read will be from the subsequent row of the
sensor RAM.
 Read Display RAM

16 byte display RAM location to be

accessed

The CPU sets up the 8279 for a read of the Display RAM by first writing this command.
The address bits AAAA select one of the 16 rows of the Display RAM.

If the AI flag is set (AI=1), this row address will be incremented after each following
read or write to the Display RAM.

Since the same counter is used for both reading and writing, this command sets the
next read or write address and the sense of the Auto-Increment mode for both
operations.
Write Display RAM

 The CPU sets up the 8279 for a write to the Display RAM by first writing this
command. After writing the command with A0=1, all subsequent writes with A0 = 0
will be to the Display RAM.

 The address and Auto-Increment functions are identical to those for the Read
Display RAM.

 However, this command does not affect the source of subsequent Data Reads; the
CPU will read from whichever RAM (Display of FIFO/Sensor) which was last
specified. If, indeed, the Display RAM was last specified, the Write Display RAM
will, nevertheless, change the Next Read location.
 Display Write Inhibit/Blanking

Inhibit Nibble A
0=> Normal Operation
1=> Inhibit or Freeze Nibble A display
Inhibit Nibble B
0=> Normal Operation
1=> Inhibit or Freeze Nibble B display

Blank Nibble A
0=> Normal Operation
1=> Blank Nibble A display

Blank Nibble B
0=> Normal Operation
1=> Blank Nibble B display

This code defaults to all zeros after a reset. Note that both BL flags must be set to blank a
display formatted with a single 8-bit port.
 Clear

The CD bits are available in this command to clear all rows of the Display RAM to a
selectable blanking code as follows :

During the time the Display RAM is being cleared (~160 μs), it may not be written to. The
most significant bit of the FIFO status word is set during this time. When the Display RAM
becomes available again, it automatically Resets.

If the CF bit is asserted (CF = 1), the FIFO status is cleared and the interrupt output line is
reset.
Also, the Sensor RAM pointer is set to row 0.
CA, the Clear All bit, has the combined effect of CD and CF; it uses the CD clearing code on
the Display RAM and also clears FIFO status. Furthermore, if resynchronizes the internal
timing chain.
End Interrupt/Error Mode Set

For the sensor matrix modes this command lowers the IRQ line and enables further
writing into RAM. (The IRQ line would have been raised upon the detection of a
change in a sensor value.

This would have also inhibited further writing into the RAM until reset).
For the N-key rollover mode - if the E bit is programmed to “1” the chip will operate in
the special Error mode.
In a microprocessor based system, when keyboard
and 7-segment LED display is interfaced using
ports or latches then the processor has to carry
the following task.

•Keyboard scanning
•Key debouncing
•Key code generation
•Sending display code to LED
•Display refreshing
Interfacing 8279 with 8085 processor:

•A typical Hexa keyboard and 7-segment LED display interfacing circuit using 8279 is shown.
Interfacing 8279 with 8 X 4 matrix keyboard

Source program:
MVI A, 00H  : Initialize keyboard/display in
encoded
OUT 81H  : scan keyboard 2 key lockout
mode
MVI A, 34H
OUT 81H  : Initialize prescaler count
MVI A, 0BH  : Load mask pattern to enable
RST 7.5
SIM  : mask other interrupts
EI  : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt

Interrupt Subroutine:
MVI A, 40H  : Initialize 8279 in read FIFO
OUT 81H  : RAM mode
IN 80H  : Read FIFO RAM (keycode)
EI  : Enable Interrupt
RET  : Return to main program
Interfacing 8279 with 8 X 8 matrix keyboard (decoded mode)

SL2
SL1
SL0

74138

8279
Interfacing 8279 with seven segment display
Interfacing 8279 with 8 seven segment display (decoded
mode)
Source program:
MVI A, 00H : Initialize keyboard/display in encoded
OUT 81H : scan keyboard 2 key lockout mode
MVI A, 34H
OUT 81H : Initialize prescaler count
MVI A, 0BH : Load mask pattern to enable RST 7.5
SIM : mask other interrupts
EI : Enable Interrupt
HERE: JMP HERE : Wait for the interrupt

Interrupt service routine

MVI A, 40H : Initialize 8279 in read FIFO RAM mode
OUT 81H
IN 80H : Get keycode
MVI H, 62H : Initialize memory pointer to point
MOV L, A : 7-Segment code
MVI A, 80H : Initialize 8279 in write display RAM mode
OUT 81H
MOV A, M : Get the 7 segment code
OUT 80H : Write 7-segment code in display RAM
EI : Enable interrupt
RET : Return to main program