Demultiplexing AD7-AD0

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 Bus Demultiplexer AD7-AD0

• Consider the timing diagram of the

instruction MOV C,A => with machine
code (4FH).

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 Bus Demultiplexer AD7-AD0

Figure 1

3
 Bus Demultiplexer AD7-AD0
• From fig 1, to run instruction MOV C, A the
high order address bus maintained as bus
address for three clock periods.
• However the low order address bus (05H)
was eliminated after first t-state.
• The address need to be latched as to
identify memory address.
• After T1, the bus AD7-AD0 now becomes
4FH.
4
• Schematic diagram to latch low order address bus.

05H

Figure 2
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 Bus Demultiplexer AD7-AD0
• In Fig 2, the AD7-AD0 bus is connected to the input of
latch buffer 74LS373.
• The ALE signal is connected to enable pin (G) at latch,
and the output control signal is grounded (OC).
• When the ALE signal is active high, the latch will act
according to the input instruction (the output changes
according to input data).
• At T1 the latch output value is 05H, and when ALE is low,
the byte data 05H is held until the new next ALE signal
activated.
• This causes the output latch is low order address
memory A7-A0 (05H).
6
 Control Signals
• It is necessary to generate two RD control
signals, one for memory and one for
peripheral.
• Similar to WR control signal; one for
writing to memory and one for writing to
output peripheral.

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 Control Signals

Figure 3: Example of schematic diagram to generate control

signals.
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Control Signals and Demultiplexing

Figure 4:the
combination of
control signals
as well as
demultiplexing
the bus system.

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Memory Interface in 8085

10
Requirement and memory structure
• There are two types of memory:
– RAM: read and write
– ROM: read only
• Figure 1a shows the R/W memory chip:
– 2048 (2k) size.
– 8 bit data input line and 8 bit data output line.
– 11 address lines, A0-A10,
– one chip select, CS.
– RD: enable output buffer (penimbal keluaran).
– WR: enable input buffer (penimbal masukan).
– The internal decoder is used to decode the internal
memory address.
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Requirement and memory structure

Figure 1 12
 Requirement and memory
structure
• Figure 1b shows the typical diagram of EPROM (Erasable
Programmable ROM):
– 4096 (4k) size.
– A quartz window on it, that use to receive direct UV light to erase
programme.
– 8 bit data output line.
– 12 address lines, A0-A11,
– one chip select, CS.
– RD: enable output buffer (penimbal keluaran).
– The internal decoder is used to decode the internal memory
address.
• The technique to interface R/W and EPROM is the same except
the EPROM does not require WR control signals.

When the chip is programmed, the quartz window has to be

covered to avoid accidental program erase.
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 Basic concept of interfacing
memory chip.
• The basic function of memory interfacing
is that the μp should be able to read from
and/or write into memory chip.
• Therefore the μp has to:
– Be able to select certain memory chip.
– Identify memory location through memory
address.
– Enable input or output buffer as to read or
write to the memory.
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 Basic concept of interfacing
memory chip.
• A few basic steps to undertake in chip
interface design are:
– Connect certain address lines from address
bus of μp to address lines at memory chip.
– Decode the rest of the address lines to
generate Chip Select signal.
– Generate control signals MEMR and MEMW.

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 Decoding the address lines
• Figure 2 shows two techniques to decode
address lines:
– Using the NAND gates.
– Using the 3-to-8 decoder.
• The output of NAND gate can be activated
when all the input A12-A15 is at logic 1.

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NAND or Decoder

Figure 2 17
 Decoding the address lines
• Using the 3-to-8 (74LS138) decoder:
– combining the input A12-A14 to obtain output at
O7 when A12= A13= A14=1.
– The enable pins E1 and E2 are enabled by
grounding them and the A15 digital signal
should be at logic 1 to enable the E3.

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74LS138 3-to-8 Line Decoder
Inputs Outputs

E1 E2 E3 C B A 0 1 2 3 4 5 6 7
1 x x x x x 1 1 1 1 1 1 1 1
x 1 x x x x 1 1 1 1 1 1 1 1
x x 0 x x x 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0

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Memory interface

Figure 3
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Reading and decoding address lines

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 Address Decoding
• Referring to figure 3:
– the logic combination at address A15-A12 must have
logic 0000 to activate the Chip Enable,
– and the address A11-A0 can have all logic
combinations either 0 or 1.
– Therefore the range of address for this chip is
0000H until 0FFFH;

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

Chip Enable Register Select

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Address Decoding 2K RAM

Address Range?
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 Address Decoding
Note: A11 is not used for RAM.

ROM RAM

Address Range ?
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Address Decoding

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 Address Decoding

ROM1
A12 A ROM2
0 CE

A13 B 3-to-8 1 CE
decoder 2
A14 C 74LS138 OE
RAM1
3
4 CE RAM2
IO/M E1 5 OE WE

E2 6 CE
7 OE WE
E3
1K RD

+5V WR
Address Range?
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