MOS AND BICMOS circuit design

processes
• MOS layers
• Design rules
• Stick diagrams
• Layout diagrams
• Examples
MOS AND BICMOS circuit design processes

• This unit provide an insight into the methods and

means for materializing circuit design in silicon
• Design processes are aided by simple concepts
such as stick diagrams and symbolic diagrams
• Key elements are design rules
• Design rules are communication link between
the designer specifying requirements and the
fabricator who materializes them.
MOS AND BICMOS Circuit Design Processes

• Design rules produce workable masklayouts

from which the various layers in silicon will be
formed or patterned
• We will discuss Lambda-based design rules
• Design rules are technology specific.
• We must find a way of capturing the topology
and layer information.
 MOS Layers
• N plus layer
• P plus layer
• Metal layers
• Polysilicon layer
• Thin oxide layer
• Thick oxide layer
• Layer information and topology should be
conveyed to fabricator.(good old method)
 Stick diagrams
• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of stick
diagram.
– To learn how to draw stick diagrams for a given MOS
circuit.

• Outcome:
– At the end of this module you will be able draw the stick
diagram for simple MOS circuits
 Stick Diagrams

Stick Diagrams
VDD
VDD
X

X
x x x
x Stick
Diagram X

Gnd Gnd

6
 Stick Diagrams

Stick Diagrams

VDD
VDD
X

X
x x x
x X

Gnd Gnd

7
 Stick Diagrams

Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information through
colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit
and the actual layout.

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 Stick Diagrams

Stick Diagrams

 Does show all components/vias.

 It shows relative placement of
components.
 Goes one step closer to the layout
 Helps plan the layout and routing

A stick diagram is a cartoon of a layout.

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 Stick Diagrams

Stick Diagrams

 Does not show

• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub
boundaries.
• Any other low level details such as
parasitics.. 10
 Stick Diagrams

Stick Diagrams – Some rules

Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 2.
When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

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 Stick Diagrams

Stick Diagrams – Some rules

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.

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 Stick diagrams
Rules for different layer contacts
 Stick Diagrams

How to draw Stick Diagrams

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Stick Diagrams

19
Stick Diagrams

Power

A Out

Ground

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 Stick Diagrams

Stick Diagrams
• Summary:

– What is stick diagram?

– Why stick diagram?
– Conventions and rules related to stick diagram.
– Drawing stick diagrams.

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Basics of Layout Design and
Design Rules
 Lambda Based Design Rules
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting
out mask
• If design rules are obeyed, masks will produce
working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping
out of area to be contacted
 Layout Design Rules
• Layout design rules describe how small features can be and how
closely they can be packed in a particular manufacturing process.
• Industrial design rules are usually specified in microns. This makes
migrating from one process to a more advanced process difficult
because not all rules scale in the same way.
• Mead and Conway popularized Lambda-based design rules based on
a single parameter, λ, which characterizes the resolution of the
process.
 Layout Design Rules
• λ is generally half of the minimum drawn transistor channel length, is the
distance between the source and drain of a transistor and is set by the
minimum width of a polysilicon wire.
– For example, a 180nm process has a minimum polysilicon width (and
hence transistor length) of 0.18 microns and uses design rules with λ =
0.09 µm
• By using lambda based design rules, they make scaling layout trivial; the same
layout can be moved to a new process simply by specifying a new value of λ.
• Designers often describe a process by its feature size. Feature size refers to
minimum transistor length, so λ is half the feature size.
 Layout Design Rules:

• The Design Rules are usually described in two ways:

– Micron Rules, in which the layout constraints such as minimum feature sizes
and minimum allowable feature separations are stated in terms of absolute
dimensions in micrometers.
– Lambda Rules, which specify the layout constraints in terms of a single
parameter(λ) that has units of µm and that can be easily scaled to different
processes.
• All widths, spacings and distances are written in the form: Value=mλ,
where ‘m’ is scaling multiplier.
• Design rules can be classified into four main types: minimum width,
minimum spacing, surround and extension.
 Design Rules - The Reality
• Manufacturing processes have
inherent limitations in accuracy and
repeatability
• Design rules specify geometry of
masks that provide reasonable yield
• Design rules are determined by
experience
 Problems - Manufacturing
• Photoresist shrinking / tearing
• Variations in material deposition
• Variations in temperature
• Variations in oxide thickness
• Impurities
• Variations between lots
• Variations across the wafer
 Problems - Manufacturing
• Variations in threshold voltage
– oxide thickness
– ion implantation
– poly variations
• Diffusion - changes in doping (variation in R, C)
• Poly, metal variations in height and width -> variation in
R, C
• Shorts and opens
• Via may not be cut all the way through
• Undersize via has too much resistance
• Oversize via may short
 Design Rules
• Under worst case misalignment and
maximum edge movement of any
feature, no serious performance
degradation should occur
 Layouts
Rules for different layer contacts
Lamda Based Design Rules:
Contd…
Contd….
Contd…
Contd…
2um design rules:
Contd…
Contd….
Contd…
 N MOSFET Layout
Drawing the N-Diffusion (Active)
 The Gate Poly:

The second step is to draw the gate. We will use a vertical polysilicon rectangle to create the
channel
 Making Active Contacts:

The next step is to make the active contacts. These contacts will provide access to the drain and source regions of the NMOS transistor.
Contd…
 Covering Contacts with Metal-1:

Active contacts in fact only define holes in the oxide (connection terminals). The actual connection to the corresponding diffusion region is made by
the Metal layer.
 The N-Select Layer:

Each diffusion area of each transistor must be selected as being of n-type or p-type. This is accomplished by a defining
the "window: of n-type (or p-type) doping (implantation), through a special mask layer called n-select (p-select).

This is the complete layout process of a NMOS transistor.

 PFET Layout:
Drawing the P-Diffusion (Active)
Draw the gate poly:
Place the contacts:
Cover contacts with Metal-1
 The P-Select Layer:

As with the NMOS transistor, the p-type doping (implantation) window over the active area must be
defined using the P-select layer.
 Drawing the N-Well:

A larger n type region (n-well) must be created, which acts like a substrate for the PMOS transistors.
 CMOS INVERTER Layout:
Placing the PMOS and NMOS transistors:

Connecting the Output: Draw a Metal-1 rectangle between NMOS and PMOS drain region contacts.
Connecting the Input:
Making a Metal-1 connection for the Input:
 Power Rails:
Draw the Power Rail in Metal-1 above the PMOS.
Draw the Ground Rail in Metal-1 below the NMOS.
 P-Substrate Contact:

Draw a P-select square next to the NMOS transistor.

Draw a P-active square inside the P-select area.
Draw the active contact square inside the p-type active
area:
Make a metal connection to ground, covering the entire
substrate contact:
N-Substrate Contact:
AND2

VDD
V DD
V DD

NOT(AB)
NOT(AB)
B A and B
A
A

B
GND
GND
GND
 NOR2

V DD
V DD

A
A
B NOT(A+B)
NOT(A+B)
B The output here is
GND connected to one
GND p-trans drain and
one n-trans drain.
 Double Metal MOS Process Rules:
• Use the second level metal for the global distribution
of power buses, that is, VDD and GND (VSS), and for
clock lines.

• Use the first level metal for local distribution of

power and for signal lines.
1.2um design rules:
Contd…
Contd…
Contd….