ECS 465: Digital Systems

Lecture Notes # 7
(A) Introduction to Sequential Circuits
(B) Latches and Flip-Flops
(C) Counter Design

SHANTANU DUTT

Department of Electrical and Computer Engineering

University of Illinois, Chicago
Phone: (312) 355-1314: e-mail: [email protected]
URL: http://www.eecs.uic.edu/~dutt

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 (A) Introduction to Sequential Circuits

• Current o/p depends on the current i/p and past history of all i/ps
seen by the circuit.

Where the relevant past history should be representable by a finite

number of classes or states
Light = Not red Light = Green
O/P = 0 O/P = 1
Reset
Red Light Encode as
No Red
Light = Red State
state = 1
O/P = 0
Encode as state=0 Light = Not green
O/P = 0
State Transition Diagram
Design Problem: Output of the circuit is 1 only if it has seen a red
light in the past and currently light is green.
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 Circuit-Level Model of a Sequential Circuit.

I/p from x0 Z0 Going to

external external
point xn-1 Combinational Zm-1 world
State Circuit
yk-1 y’k-1
bits of
seq. ckt. y0 y’0

Current Memory Next

State State
Unit

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 (B) Latches and Flip-Flops

Components to store bits ( latches or flip flops )

1) Problem: can’t store
1 0 new data
1 1
Cascade of inverter
LD
2)
LD A
LD
0

I/P 1/0 O/P

LD A
Will conduct when
A=1, and open when
A=0
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 Another storage element:
NOR gates ( R-S latch )
3) Cross coupled NOR gates ( R-S latch ) R (Reset)
Q
Q
0
Q Q
Q
1
R=0 0 S (Set)
S=1
B
Property of a NOR gate A B  B
B

A=0
When one I/P of NOR is 0, it acts like an inverter.
When one I/P is 1, then O/P=0.
Different I/P conditions for R-S latch:
i) R=S=0, current I/P is stored indefinitely
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Hold ( becomes cascade of inverters)
ii) R=1, S=0, when we want to store a 0 in the R-S latch.
Q=0, Q  1
iii) R=0, S=1, when we want to store a 1 in the latch.
Q=1, Q  0
iv) R=1, S=1; Forbidden inputs!
Both Q = 0, Q  0 : Q and its complement have the same value !
Will play havoc in the rest of the logic circuit.
Transit to: R=0, S=0.

R=1, S=1, both Q and Q and 0.

0 0 O/P oscillates.
R=10 Q
0 Oscillates
0 01
Q
between 1 and 0
1
 when we transit from 6
01
S=10 R=S=1 to R=S=0.
 From R, S = 1, 1 transit to R=0, S=1
then Q,Q transit to 1, 0 ( correctly )
From R, S = 1, 1 transit to R=1, S=0
then Q, Q correctly transit to 0, 1
Two implementations for R-S latch:

Cross-coupled NOR Cross-coupled NAND

R R
Q Q

Q Q

S S

Hold State R=S=0 Hold State R=S=1

R=0, S=0
R=1, S=1
Q
Forbidden I/Ps
Q 7
 4) The D-Latch
R
R1 Q

enb
R-S Clocked Latch
Latch Q (level-sensitive clock latch)
D S1 — see terminology defined
S
later.
D=1, S=1, R=0 enb=1
Q=1, Q  0
D=0, S=0, R=1
enb=1
Q=0, Q  1
enb=0 R1,S1=0 (hold state)

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5) The J-K Latch:
— Proposed to get rid of the forbidden I/P problem of R-S
i) J=1, K=0: (a) Let Q=1, Q  0  R=0,S=0
 Hold state of R-S  Q=1, Q  0
(b) Let Q=0, Q  1, R=0, S=1  Q=1, Q  0
ii) J=0, K=1  Q=0, Q  1 using a similar analysis
iii) J=K=0  Hold state
iv) J=K=1, suppose Q=1,Q =0
 R=1, S=0  Q=0, Q =1
 S=1, R=0  Q=1, Q =0
This type of toggling continues as long as J=K=1, and the latch
is enabled ( CLK=1 below )
Q 10 10
K R
R Q
CLK
R-S
J 1
S Q
Q 01 01 9
Latch classification with respect to response to “control signal”
Terminology: Note that the terminology below applies to all types of latches:
R-S, D, J-K, T, etc., though the examples are given for the R-S latch.
i) Transparent Latch: O/P responds to latch I/Ps without any enable or clock signal.
R Q
Symbol: R Q
Q S Q

S
Clock:
Fixed frequency alternating 1 and 0 signal
ii) Clocked or Level-Sensitive Latch:
R O/P responds to I/Ps only when enb or
Q
clock is at a pre-determined level (high
Clock
or
or low — In this example, it is High)
Q
enb
S Symbol: R Q R Q
or
S Q S Q
CLK 10
(high enable) CLK (low enable)
iii) Edge-Triggered Flip-Flop (FF) or simply Flip-Flop
O/P will respond to I/Ps only at either:
(a) the positive or rising edge of the enb/clock signal (positive
edge-triggered FF), or Symbol: R Q
S Q
CLK
(b) the negative or falling edge of the enb/clock signal (negative
edge-triggered FF). Symbol: R Q
S Q

CLK
Clock:
O/P resp. period for
a low-enable/clock
level sensitive latch
O/P response
O/P response O/P response
period for a
period for a period for a
positive
negative HIGH-enable/clock
edge-
edge-triggered level-sensitive 11
triggered
FF latch
FF.
 Setup Times and Hold Time of FFs and Latches
• Assume, positive edge-triggered D-FF
THold relates to propagation delay
of another part of circuit.
D

CLK

TSetup relates to propagation delays of

The high point of various gates in the FF.
the CLK determines the positive edge’s arrival.
• If negative edge-triggered
TSetup THold
D

CLK
Negative edge arrival
• If D-Latch is high-level sensitive: Tsetup and Thold have to be around the negative edge
of clock (more specifically, when the clock begins to go low), similar to negative edge-triggered.
•If D-Latch is low-level sensitive: Tsetup and Thold have to be around the positive 12
edge of clock, similar to positive edge-triggered.
 Solutions to Race Condition Problem with Level Sensitive Latches
Solution 1: Master-Slave FF:
Q
1 Q
R Qs
J Qm
P R
1 R-S 1
1
Latch R-S
0 P 0
K Qm Qs
S 0 S Q
0
CLK

Master R-S is level sensitive. Slave R-S is level sensitive.

Master-Slave J-K is a solution to race-condition problem: Any change in Q, Q
during CLK=0 is not propagated to P, P and hence back to Q, Q during the
same CLK=0. Any change to Q, Q will occur in next CLK=0 period.
J Q Master-Slave J-K works similar
J-K
to a J-K latch: E.g. Let
K M-S Q J=1, K=1, CLK=1
Q=1, Q =0  P =1 , P=0
When CLK=0
(O/P responds when CLK goes Q=0, Q =1 13
From 1 to 0)
 Assume D=1
D
Solution 2: Edge-Triggered FF: D D 0R
D=1=S
D
HoldsD when
Q=1, Q  0
D R
clock goes low Q =D
Clk=0
R Q D
0 Q
S
Clk=1 D
Q Q responds to
S internal S signal;
0 D D Q responds to
Holds D when
clock goes low internal R signal.
D D
CLK
D D
When CLK is 1 D I/P is O/P appears (Q=D)
internally sampled but D
does not appear at the O/P. R
0 Q O/P is held (changing D does not
Clk=0
cause any change in internal
Q signals in the FF or in its output)
S
D

D 0 14
 Characteristic Equations of Latches/FFs
The next O/P Q+ defined in terms of the current O/P Q and the I/P.
(FF/Latch is the simplest possible sequential ckt.)

1) R-S Latch— Truth Table:

Values at time t
S(t) R(t) Q(t) Q+ = Q( t+ )
0 0 0 0
Hold
0 0 1 1
0 1 0 0
0 1 1 0 Reset
1 0 0 1
Set
1 0 1 1
1 1 0 x
Forbidden
1 1 1 x

Q(t)\SR 00 01 11 10 Q+= S+ R Q
0 0 0 x 1 (Characteristic equation)
1 1 0 x 1 15
Similarly: Characteristic Equations of

2) J-K, Q+ = Q K + Q J.
Symbol: Q
3) D-FF, Q = D+
T
4) Toggle FF/Latch Q = Q T + QT
+
Q
or T-FF / Latch

Whenever I/P T is high,

the FF will toggle, i.e., Q+ = Q.
When T=0, Q+=Q.

Of course, these characteristic equations come into play only

when the FF/Latch is enabled.

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 Excitation Table

— Reversed Truth Table

— What the inputs to FFs should be for given output
transitions (Q  Q+)

Q Q+ R S J K T D
0 0 x 0 0 x 0 0
0 1 0 1 1 x 1 1
1 0 1 0 x 1 1 0
1 1 0 x x 0 0 1

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 — Conversion between FFs
Example: J-K to D This should
behave like a
D-FF.

D J Q
Logic
Q
K

CLK

D D
Q 0 1 Q
O/P function = J Function = K x x
J=D
0 0 1 K= D
D D
1 x x 1 0
Map the D,Q input combination to a QQ+ transition
and then map this to J-K excitation required.
Thus, when D=1, Q=0, Q+=1  J,K = 1,x
D=0, Q=0, Q+=0  J,K = 0,x D-FF
D=1, Q=1, Q+=1  J,K = x,0
D=0, Q=1, Q+=0  J,K = x,1. J Q
D Q
K
CLK 18
 Example 2: D  J-K
should work like a J-K
Excitation Table for D
Q Q+ D J K Q Q+
00 0 0 0 0 0 J D Q
01 1 0 0 1 1 Logic
0 1 0 0 K Q
10 0
0 1 1 0
11 1 1 0 0 1
JQ CLK
JK 1 0 1 1
00 01 11 10
Q
1 1 0 1 TT for J-K
0 0 0 1 1
1 1 1 0
1 1 0 0 1
KQ
Function is D  JQ  K Q J-K FF/Latch
Q
D Q
K Q
J Q

CLK
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 (C) Counter Design
• A counter is a special case of an FSM that cycles through its states
on receiving triggering clock pluses.
• It does not have any external data I/Ps.
100 No external I/Ps
Reset E
A Counter O/P
000 011
D Logic Next State
001 bits
B
C 010

FFs
n n

CLK
• The states need to be encoded by binary bits.
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 State Transition Diagram and Table for a 3-bit Binary Up-Counter

Reset Synthesis (3-Bit Up Counter) Output Toggle Flip-Flop

Input
Present State Next State Inputs
000 111
C B A C+ B+ A+ TC TB TA
001 110
0 0 0 0 0 1 0 0 1
010 101 0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
011 100 0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
(a) State Transition
1 1 0 1 1 1 0 0 1
Diagram
1 1 1 0 0 0 1 1 1
(b) State Transition Table (What next state
FF Excitation Table Revisited will be given the
Q Q+ R S J K T D current state.)
0 0 x 0 0 x 0 0
0 1 0 1 1 x 1 1
1 0 1 0 x 1 1 0
1 1 0 x x 0 0 1 21
Excitation table for R-S, J-K, T, and D Flip-Flops
From excitation table for FF inputs, get K-map for the FF inputs.

CB
CB
00 01 11 10 A 00 01 11 10
A
0 0 0 0 0
0 1 1 1 1
1 1 0 1 1 0
1 1 1 1
TA=1 TC=AB
CB
A 00 01 11 10 K-maps for Up-Counter Using Toggle
0 0 0 0 0 Flip-Flops.
1 1 1 1 1
TB=A

Obtain logic expr. for FF I/Ps (as functions of current state bits A,
B, C, --- A=QA, B=QB, C=QC) and realize the counter

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 Counters with More Complex Sequencing (Non-Consecutive Binary Outputs)
Present State Next State

000 110 C B A C+ B+ A+
0 0 0 0 1 0
010 101 0 0 1 x x x
0 1 0 0 1 1
011 0 1 1 1 0 1
1 0 0 x x x
State Transition 1 0 1 1 1 0
Diagram 1 1 0 0 0 0
Implementation Using J-K FFs: 1 1 1 x x x
State Transition Table
Present Next Remapped Next
State State State
C B A C B+
+
A+ JC KC JB KB JA KA Q Q+ J K
0 0 0 0 1 0 0 x 1 x 0 x
0 0 0 x
0 0 1 x x x x x x x x x
0 1 0 0 1 1 0 x x 0 1 x
0 1 1 x
0 1 1 1 0 1 1 x x 1 x 0 1 0 x 1
1 0 0 x x x x x x x x x 1 1 x 0
1 0 1 1 1 0 x 0 1 x x 1 Q   JQ  K Q
1 1 0 0 0 0 x 1 x 1 0 x J-K Flip-Flop Excitation Table
1 1 1 x x x x x x x x x 23
State Transition Table and Remapped Next-State Functions
 Next State Functions
JC  A KC  A
JB 1 KB  A  C
J A  BC KA  C
CB CB
00 01 11 10 A 00 01 11 10
A x x 1 x
0 0 0 x x 0 KC
JC
1 x 1 x x x 0
1 x x
CB CB
A 00 01 11 10 A 00 01 11 10
0 1 x x x 0 x 0 1 x
JB KB
1 x x x 1 1 x 1 x x
CB CB
A 00 01 11 10 00 01 11 10
A
0 0 1 0 x JA 0 x x x x KA
1 x x x x 1 x 0 x 1
Remapped K-Maps for J-K Implementation. 24
 Actual Implementation ( Using J-K)

C B JA A
A J Q J Q J Q
CLK CLK CLK
K Q K Q K Q
A C KB B C A
Count
signal

A B
KB JA
C C

J-K Flip-Flop Implementation of 3 Bit Counter.

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