Lecture 1: Introduction

Chapter 01: Introduction to Microprocessor

Concept of Microprocessor
• The microprocessor is one of the most important components of a
digital computer.

• It acts as the brain of the computer system.

• As technology has progressed, microprocessors have become faster,

smaller and capable of doing more work per clock cycle.
Concept of Microprocessor
• Definition:

Microprocessor is the controlling unit or CPU of a micro-computer,

fabricated on a very small chip capable of performing ALU operations
and communicating with the external devices connected to it.
Concept of Microprocessor

Microprocessor:
• The central processing unit built on a single IC is called
Microprocessor.
• A microprocessor (sometimes abbreviated as μP) is a digital electronic
component with miniaturized transistors on a single semiconductor
integrated circuit (IC).
• One or more microprocessors typically serve as a central processing
unit (CPU) in a computer system or handheld device.
Concept of Microprocessor

A Micro-Computer
• As the name implies, microcomputers are small computers.
• The block diagram of the microcomputer is similar to the computer except that
the central processing unit of the microcomputer is contained in a single IC called
the microprocessor.

Microprocessor
Input Unit (ALU+ Register Output Unit
array+ control unit)

Memory
Concept of Microprocessor

Microcomputer:
• A digital computer, in which one microprocessor has been provided to
act as a CPU, is called Microcomputer.
• A desktop computer, laptop, notebook, palmtop, etc. contain one
microprocessor to act as a CPU and hence they come under the
category of microcomputer.
• The term microcomputer is generally synonymous with personal
computer.
Concept of Microprocessor

Multiprocessor System:
• The CPU of a large powerful digital computer contains more than one
microprocessor.
• High-end powerful servers, mainframe computers, supercomputers,
etc. contain more than one microprocessor to act as CPU.
• A computer whose CPU contains more than one microprocessor is
called Multiprocessor System.
Concept of Microprocessor

Microcontroller:
• A highly integrated chip that contains all the components such as
CPU, RAM, some form of ROM, I/O ports, and timers is called
Microcontroller.
• Unlike a general-purpose computer, which also includes all of these
components, a microcontroller is designed for a very specific task to
control a particular system.
Functions of a Microprocessor
• The processor first fetches and instruction from the main memory.
• The instruction is then decoded to determine what action is required to
be done.
• Based on instruction the processor fetches, if required, data from main
memory or I/O module.
• The instruction is then executed which may require performing arithmetic
or logical operations on data.
• In addition to execution, CPU also supervises and controls/I/O devices.
• Finally, the results of an execution may required transfer of data to
memory or an I/O Module.
Microprocessor Characteristics

Instruction Set: The set of instructions that a microprocessor can

understand.
Bandwidth: The number of bits processed in a single instruction.
Capability: It depends upon the number of instructions and capability
of each instruction.
Microprocessor Characteristics

Clock Speed:
• The clock speed determines the number of operations per second the
processor can perform.
• Clock speeds are expressed in megahertz (MHz) or gigahertz (GHz).
• It is also called Clock Rate.
Microprocessor Characteristics

Word Length:
• It depends upon the width of internal data bus, registers, ALU etc.
• An 8-bit microprocessor can process 8 bit data at a time.
• The word length ranges from 4 bits for small microprocessor, to 64
bits for high-end microcomputers.
Microprocessor Characteristics

Width of Data Bus: This is the size of the data bus. It defines the
number of bits that can be transferred through data bus.

Width of Address Bus: This parameter decides the memory addressing

capability of the microprocessor. The maximum size of the memory unit
is decided by this parameter.
Microprocessor Characteristics

Input/output Addressing Capability:

The maximum number of the input/output ports accessed by the
microprocessor depends upon the width of the input/output address
provided in the input/output instruction.
Microprocessor Characteristics

Data Types: The microprocessor handles various types of data formats

like binary, BCD, ASCII, signed and unsigned numbers.
Interrupt Capability:
• Interrupts are used to handle unpredictable and random events in the
microcomputer.
• It is used to interrupt the microprocessor.
• Interrupt driven input/output improves the throughput of a system.
Lecture 2: Evolution and Types of
Microprocessor
Evolution of Microprocessor
• The years of development of microprocessors are divided into five generations:
• 1.The First Generation (1971-73)
• 2. The Second Generation (1974-78)
• 3. The Third Generation (1979-80)
• 4. The Fourth Generation (1981-95)
• 5. The Fifth Generation (1995-Till date)
 
 1. The First Generation(1971-73)
• Intel corporation introduced 4004, the first microprocessor in 1971. It is
evolved from the development effort designing a calculator chip.
• There were three other processors in the market during the same period:
-Rockwell international's PPS-4 (4 bits)
-Intel's 8008 (8 bits)
-National Semiconductor's IMP-16 (16 bits)
• They were fabricated using P-MOS(P-channel Metal Oxide
Semiconductor) technology which provided low cost, slow speed and low
output currents.
• They were not compatible with Transistor-Transistor Logic(TTL).
1. The First Generation (1971-73)
• The instructions of these microprocessors were processed serially,
they fetched the instruction, decoded and then executed it.
  2. The Second Generation (1974-78)

• This generation marked the beginning of very efficient 8-bit

microprocessors. Some of the popular processors were:
• Motorola's 6800 and 6809
• Intel's 8085
• Zilog's Z80
They were manufactured using N-MOS(N-channel Metal Oxide
Semiconductor) technology.
This technology offered faster speed and higher density than P-MOS. It
is Transistor-Transistor Logic(TTL) compatible.
  2. The Second Generation (1974-78)
• The second generation of the microprocessor is defined by
overlapped fetch, decode and execute the steps. 
• When the first instruction is processed in the execution unit, then the
second instruction is decoded and the third instruction is fetched.
   3. The Third Generation (1979-80)

•This age was dominated by 16-bits microprocessors.

•Some of them were:
•Intel's 8086/80186/80286
•Motorolla's 68000/68010
•They were designed using H-MOS(High-Speed MOS ). H-MOS provides
some advantages over N-MOS as :
- speed-power-product of H-MOS is four times better than that of N-MOS.
- H-MOS can accommodate twice the circuit density compared to N-MOS.

•Intel used H-MOS technology to recreate 8085A and named it as 8085AH

with a higher price tag.
   4. The Fourth Generation (1981-95)
The fourth generation microprocessors are entered with outstanding design
with a million transistors.
• This era marked the beginning of 32 bit microprocessors.
-Intel introduced 432, which turned out a bit problematic.
-Then a clean 80386 was launched.
-Motorolla introduced 68020/ 68030.
They were fabricated using low-power version of H-MOS technology called HC-
MOS.
Motorolla introduced 32-bit RISC(Reduced Instruction Set Computing)
processors called MC88100.
  5. The Fifth Generation (1995-Till date)

• This age's emphasis is on introducing chips that carry on-chip

functionalities and improvements in the speed of memory and input
devices along with introduction of 64-bit microprocessors.
• Intel leads the show here with Pentium, Celeron and recent dual and
quad core like processors working with up to 3.5 GHz speed.
  History of Microprocessor
MP Name Introduced Year Data Bus Address Bus
4004 1971 4 8
8008 1972 8 8
8080 1974 8 16
8085 1977 8 16
8086 1978 16 20
80186 1982 16 20
80286 1983 16 24
80386 1986 32 32
  History of Microprocessor
MP Name Introduced Year Data Bus Address Bus
80486 1989 32 32
Pentium 1993-Onwards 32
Core Solo 2006 32
Dual Core 2006 32
Core 2 Duo 2006 32
Core 2 Quad 2008 32
Core i3 2010 64
Core i5 2009 64
Core i7 2008 64
  Types of Microprocessors

• A microprocessor can be classified into three categories

1. RISC Processors
2. CISC Processors
3. Special Processors
  Types of Microprocessors (Cont.)
• RISC Processor
• RISC stands for Reduced Instruction Set Computer. It is designed to reduce the
execution time by simplifying the instruction set of the computer. Some of the
RISC processors are −
• Power PC: 601, 604, 615, 620
• DEC Alpha: 210642, 211066, 21068, 21164
• MIPS: TS (R10000) RISC Processor
• PA-RISC: HP 7100LC
  Types of Microprocessors (Cont.)
Characteristics of RISC
• The major characteristics of a RISC processor are as follows −
• It consists of simple instructions.
• It supports various data-type formats.
• It utilizes simple addressing modes and fixed length instructions for pipelining.
• It supports register to use in any context.
• One cycle execution time.
• “LOAD” and “STORE” instructions are used to access the memory location.
• It consists of larger number of registers.
• It consists of less number of transistors.
  Types of Microprocessors (Cont.)
CISC Processor
CISC stands for Complex Instruction Set Computer. It is designed to minimize the
number of instructions per program, ignoring the number of cycles per
instruction. The emphasis is on building complex instructions directly into the
hardware.
• Some of the CISC Processors are −
• IBM 370/168
• VAX 11/780
• Intel 80486
  Types of Microprocessors (Cont.)
Characteristics of CISC
• Variety of addressing modes.
• Larger number of instructions.
• Variable length of instruction formats.
• Several cycles may be required to execute one instruction.
• Instruction-decoding logic is complex.
• One instruction is required to support multiple addressing modes.
  Types of Microprocessors (Cont.)
Special Processors
• These are the processors which are designed for some special purposes. Few of
the special processors are briefly discussed −
Coprocessor
• A coprocessor is a specially designed microprocessor, which can handle its
particular function many times faster than the ordinary microprocessor.
For example − Math Coprocessor.
• Some Intel math-coprocessors are −
• 8087-used with 8086
• 80287-used with 80286
• 80387-used with 80386
  Types of Microprocessors (Cont.)
Input/Output Processor
• It is a specially designed microprocessor having a local memory of its own,
which is used to control I/O devices with minimum CPU involvement.
For example −
• DMA (direct Memory Access) controller
• Keyboard/mouse controller
• Graphic display controller
• SCSI port controller
Lecture 3: Architecture of Intel 8086
Microprocessor
 Main Features of 8086
1. 8086 is a 16-bit microprocessor.
2. 8086 has a 16-bit data bus.
3. 8086 has a 20-bit address bus which means it can address up to 220= 1MB memory location
4. Frequency range of the 8086 is 6-10 MHz.
5. The Intel 8086 is designed to operate in two modes, namely the minimum mode and the
maximum mode.
6. The 8086 works in a multiprocessor environment.
7. It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
8. It fetches up to six instruction bytes (4 instruction bytes for 8088) from memory and queue
stores them in order to speed up instruction execution.
9. It requires +5 V power supply.
10.It uses a 40-pin dual in line package.
11.It has 256 interrupts.
  Internal Architecture of Intel 8086
Intel 8086 Microprocessor

8086 microprocessor has two units.

• Bus Interface Unit (BIU).
• Execution Unit (EU)
They are dependent and get worked by each other.
Intel 8086 Microprocessor

• We can consider two operations to make it understand:

1.ADD AL, BL
2.ADD AL, o5H
Bus Interface Unit(BIU)
BIU performs the following functions-
• It generates the 20 bit physical address for memory access.
• It fetches instruction from memory.
• It transfers data to and from the memory and I/O.
• It supports pipelining using the 6 byte instruction queue
Execution Unit (EU)
Execution Unit (EU) performs the following functions-
• It fetches instructions from the Queue in BIU, decodes and executes
them.
• It performs arithmetic, logic and internal data transfer operations
within the microprocessor.
• It sends request signals to the BIU to access the external module.
Main Components of Bus Interface Unit (BIU)
The main components of the BIU are as follows:
 4 Segment Registers
 Instruction Pointer
 Address Generation Circuit and
 A prefetch queue
 Main Components of BIU (Cont.)
Segment registers-
• CS register: CS holds the base address for the Code Segment. All programs are stored in
the Code Segment. CS is multiplied by 10H to give the 20 bit physical address of the Code
Segment. E.g. If CS = 4321H then CS x 10H = 43210H→ Starting address of Code
Segment.
• DS register: DS holds the base address for the Data Segment. It is multiplied by 10H to
give the 20 bit physical address of the Data Segment. E.g. If DS = 4321H then DS x 10H =
43210H→ Starting address of Data Segment.
• SS register: SS holds the base address for the Stack Segment. It is multiplied by 10H to
give the 20 bit physical address of the Stack Segment. E.g. If SS = 4321H then SS x 10H =
43210H→ Starting address of Stack Segment.
• ES register: ES holds the base address for the Extra Segment. It is multiplied by 10H to
give the 20 bit physical address of the Extra Segment. E.g. If ES = 4321H then ES x 10H =
43210H→ Starting address of Code Segment.
Main Components of BIU (Cont.)
Instruction Pointer (IP)-
• It is a 16 bit register. It holds offset of the next instructions in the
Code Segment.
• Address of the next instruction is calculated as CS x 10H + IP.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch occurs
Main Components of BIU (Cont.)
Address Generation Circuit-
The BIU has a Physical Address Generation Circuit. It generates the 20
bit physical address using Segment and Offset addresses using the
formula: Physical Address = Segment Address x 10H + Offset Address
Main Components of BIU (Cont.)
6 Byte Pre-fetch Queue:
• It is a 6 byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing
the current instruction is called pipelining.
• Gets flushed whenever a branch instruction occurs.
 Main Components of Execution Unit (EU)
The main components of the EU are as follows:
• General purpose registers-
• 8086 microprocessor has four 16 bit general purpose registers AX, BX, CX and DX.
These are available to the programmer for storing values during programs. Each of
these can be divided into two 8 bit registers such as AH, Al; BH, BL; etc. Beside their
general use, these registers also have some specific functions.
• AX register (16 bits): It holds operands and results during multiplication and division operations.
All I/O data transfers using IN and OUT instructions use A register (AL/AH or AX). It functions as
accumulator during string operations.
• BX register (16 bits): It holds the memory address (offset address) in indirect addressing modes.
• CX register (16 bits): It holds count for instructions like loop, rotate, shift and string operations.
• DX register (16 bits): It is used with AX to hold 32 bit values during multiplication and division. It
is used to hold the address of the I/O port in indirect I/O addressing mode.
Main Components of EU (Cont.)
Special purpose registers-
• Stack Pointer (SP 16 bits): It holds offset address of the top of the Stack.
Stack is a set of memory locations operating in LIFO manner. Stack is present in
the memory in Stack Segment. It is used during instructions like PUSH, POP,
CALL, RET etc.
• Base Pointer (BP 16 bits): BP can hold offset address of any location in the
stack segment. It is used to access random locations of the stack.
• Source Index (SI 16 bits): It is normally used to hold the offset address for
Data Segment but can also be used for other segments using Segment
Overriding. It holds offset address of source data in Data Segment during string
operations.
• Destination Index (DI 16 bits): It is normally used to hold the offset address
for Extra Segment but can also be used for other segments using Segment
Overriding. It holds offset address of destination in Extra Segment during string
Main Components of EU (Cont.)
• ALU (Arithmetic Logic Unit) - It has a 16 bit ALU. It performs 8 and 16
bit arithmetic and logic operations.
• Operand register- It is a 16 bit register used by the control register to
hold the operands temporarily. It is not available to the programmer.
Main Components of EU (Cont.)
• Instruction Register and Instruction Decoder- The EU fetches an
opcode from the queue into the instruction register. The instruction
decoder decodes it and sends the information to the control circuit
for execution.
Offset for the Specific Segment

Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Address in the stack
ES BX, DI, SI Address of destination data
(for string operations)
Question
The contents of the following registers are
• CS=1111 H
• DS=3333 H
• SS=2526 H
• IP=1232 H
• SP=1100 H
• DI=0020 H
Calculate the corresponding physical addresses for the address
bytes in CS, DS and SS
Solution
1. CS=1111 H
The base address of the code segment is 11110 H
Effective address of memory is given by 11110 H + 1232 H
=12342 H
2. 33350 H
3. 26360 H
Main Components of EU (Cont.)

Flag register (16 bits)-

• It has 9 flags.
• These flags are of two types: 6 Status flags namely carry flag, parity flag,
auxiliary carry flag, zero flag, sign flag, overflow flag and 3 Control flags
namely trap flag, interrupt flag and direction flag.
• Status flags are affected by the ALU after every arithmetic or logic
operation. They give the status of the current result.
• The Control flags are used to control certain operations. They are
changed by the programmer.
Flag Register
Auxiliary Carry Flag Carry Flag

This is set, if there is a carry from the This flag is set, when there is
lowest nibble, i.e, bit three during a carry out of MSB in case of
addition, or borrow for the lowest addition or a borrow in case of
nibble, i.e, bit three, during subtraction. subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation is the computation or byte of the result contains even
negative comparison performed by an number of 1’s ; for odd number
instruction is zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

Trap Flag
Over flow Flag
If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
interrupts after the execution of
signed operation and more than 15-bits in size in case of 16-bit
each instruction
sign operations, then the overflow will be set.
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing
Otherwise, the string is processed from the highest address IF disables these interrupts.
towards the lowest address, i.e., auto decrementing mode. 56
Flag Register Calculation
• Example:
1. Identify flag registers for the following operations of Hexadecimal
numbers:
• i. 41+4F
• ii. 37+01
• iii. 9E+D3
Flag Register Calculation (Solution)
• Example:
1. Flag registers for the following operations of Hexadecimal numbers:
• i. 41+4F (CF=0, SF=1, PF=1, ZF=0, OF=1, AF=1)

• ii. 37+01 (CF=0, SF=0, PF=0, ZF=0, OF=0, AF=0)

• iii. 9E+D3 (CF=1, SF=0, PF=1, ZF=0, OF=1, AF=1)

 8086 Microprocessor Registers

8086 registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
categorized into
groups
OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

59
Lecture 5: Addressing Modes of 8086
Addressing Mode
• The addressing mode is the method to specify the operand of an
instruction. The job of a microprocessor is to execute a set of
instructions stored in memory to perform a specific task. Operations
require the following:
• The operator or opcode
• The operands
• An assembly language program instruction consists of two parts
Example: ADD 7,8

Opcode Operand
Addressing Mode
• IMPORTANT TERMS
• Starting address of memory segment.
• Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and
index.
• Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
• Base: Contents of base register, BX or BP.
• Index: Content of index register SI or DI.
 Types of 8086 Addressing Mode
The 8086 has 8 basic addressing modes:
1) Immediate addressing mode
2) Register addressing mode
3) Direct memory addressing mode
4) Register based indirect addressing mode
5) Register relative addressing mode
6) Indexed addressing mode
7) Base indexed addressing mode
8) Relative based indexed addressing mode
9) Implied addressing mode
Types of Addressing Mode
1) Immediate addressing mode-
• In this mode, the operand is specified in the instruction itself.
Instructions are longer but the operands are easily identified.
• Example:
• MVI CL, 12H
MOV CL, 12H

• This instruction moves 12 immediately into CL register. CL ← 12H

 Types of Addressing Mode
2) Register addressing mode-
• In this mode, operands are specified using registers. This addressing
mode is normally preferred because the instructions are compact and
fastest executing of all instruction forms.
• Registers may be used as source operands, destination operands or both.
• Example:
• MOV AX, BX
• ADD AX, BX
• This instruction copies the contents of BX register into AX register.
AX ← BX
Types of Addressing Mode
3) Direct memory addressing mode
• In this mode, address of the operand is directly specified in the
instruction. Here only the offset address is specified, the segment being
indicated by the instruction.
• Example:
• MOV CL, [4321H]
• This instruction moves data from location 4321H in the data segment
into CL.
• The physical address is calculated as
• DS * 10H + 4321
• Assume DS = 5000H
• ∴PA = 50000 + 4321 = 54321H
• ∴CL ← [54321H]
Types of Addressing Mode
4) Register based indirect addressing mode
• In this mode, the effective address of the memory may be taken directly
from one of the base register or index register specified by instruction. If
register is SI, DI and BX then DS is by default segment register.
• If BP is used, then SS is by default segment register.
• Example:
• MOV CX, [BX]
• This instruction moves a word from the address pointed by BX and BX + 1
in data segment into CL and CH respectively.
• CL ← DS: [BX] and CH ← DS: [BX + 1]
• Physical address can be calculated as DS * 10H + BX.
Types of Addressing Mode
5) Register relative (Based) addressing mode-
• In this mode, the operand address is calculated using one of the base
registers and an 8 bit or a 16 bit displacement.
• Example:
• MOV CL, [BX + 04H]
• This instruction moves a byte from the address pointed by BX + 4 in data
segment to CL.
• CL ← DS: [BX + 04H]
• Physical address can be calculated as DS * 10H + BX + 4H.
Types of Addressing Mode
6) Indexed addressing mode-
In this addressing mode, the operands offset address is found by adding the
contents of SI or DI register and 8-bit/16-bit displacements.
Example

MOV BX, [SI+16], ADD AL, [DI+16]

Types of Addressing Mode
7) Base indexed addressing mode-
• Here, operand address is calculated as base register plus an index
register.
• Example:
• MOV CL, [BX + SI]
• This instruction moves a byte from the address pointed by BX + SI in
data segment to CL.
• CL ← DS: [BX + SI]
• Physical address can be calculated as DS * 10H + BX + SI.
Types of Addressing Mode
8) Relative based indexed addressing mode
• In this mode, the address of the operand is calculated as the sum of base
register, index register and 8 bit or 16 bit displacement.
• Example:
• MOV CL, [BX + DI + 20]
• This instruction moves a byte from the address pointed by BX + DI + 20H
in data segment to CL.
• CL ← DS: [BX + DI + 20H]
• Physical address can be calculated as DS * 10H + BX + DI + 20H.
Types of Addressing Mode
9) Implied addressing mode
• In this mode, the operands are implied and are hence not specified in
the instruction.
• Example:
• STC
• This sets the carry flag.
Other Addressing Mode
String Addressing Mode
Employed in string operations to operate on string data.

• The effective address (EA) of source data is stored in SI register and the EA of destination is stored in DI register.

• Segment register for calculating base address of

• source data is DS and that of the destination data is ES

•Example: MOVS BYTE

• Operations:

• Calculation of source memory location:

• EA = (SI) BA = (DS) x 1610 MA = BA + EA

• Calculation of destination memory location:

• EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE

• (MAE)  (MA)

• If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1

• If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
Other Addressing Mode
Addressing Modes for Accessing I/O Ports
Standard I/O uses port addressing modes. Two types:
i) I/O mode (direct):
 
Port number is an 8 bit immediate operand. Example: OUT 05 H, AL
Outputs [AL] to 8 bit port 05 H
 
ii) I/O mode (indirect):
 
The port number is taken from DX.
Example 1: IN AL, DX
 If [DX] = 5040
 8 bit content by port 5040 is moved into AL.
Example 2: IN AX, DX
 Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
Offset for the Specific Segment

Segment Offset Registers Function

CS IP Address of the next instruction
DS BX, DI, SI Address of data
SS SP, BP Address in the stack
ES BX, DI, SI Address of destination data
(for string operations)
Lecture 6: Instruction Set of 8086
Microprocessor
Instruction Set of 8086
The 8086 microprocessor supports 8 types of instructions
1) Data Transfer Instructions
2) Arithmetic Instructions
3) Bit Manipulation Instructions
4) String Instructions
5) Program Execution Transfer Instructions (Branch & Loop Instructions)
6) Processor Control Instructions
7) Iteration Control Instructions
8) Interrupt Instructions
Data Transfer Instruction

1) Data Transfer Instructions

These instructions are used to transfer the data from the source
operand to the destination operand. Following are the list of
instructions under this group −
Data Transfer Instruction
Instruction to transfer a word
• MOV − Used to copy the byte or word from the provided source to
the provided destination.
• PUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided
location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.
- Is equivalent to MOV AL, [AL] [BX]
Data Transfer Instruction
Instructions for input and output port transfer
• IN − Used to read a byte or word from the provided port to the accumulator.
Fixed port addressing: IN AX, 38H
OUT 38H, AL
Variable port Addressing: IN AL, DX; IN AX, DX; OUT DX, AL; OUT DX, AX
• OUT − Used to send out a byte or word from the accumulator to the provided
port.
• Instructions to transfer the address
• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.
Data Transfer Instruction
Instructions to transfer flag registers
• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
PUSHF − Used to copy the flag register at the top of the stack.
• POPF − Used to copy a word at the top of the stack to the flag
register.
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE
MOV D, S D=S MOV AX, [SI]
PUSH D pushes D to the stack PUSH DX
POP D pops the stack to D POP AS
XCHG D, S exchanges contents of D XCHG [2050], AX
and S
IN D, S copies a byte or word IN AX, 38H
from S to D IN AX, DX
OUT D, S copies a byte or word OUT 05, AL
from D to S
Data Transfer Instruction

OPCODE OPERAND EXPLANATION EXAMPLE

LEA D, S Load effective LEA AX, [BX]
address
LDS D, S Load register and DS LDS BX, [CX]
LES D, S Load register and ES LES BX, [CX]
Data Transfer Instruction
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

translates a byte in AL XLAT

XLAT none using a table in the equivalent to MOV AL,
memory [AL] [BX]

loads AH with the lower

LAHF none byte of the flag register LAHF
AHFlag register(0-7)
stores AH register to
lower byte of the flag
SAHF none register SAHF
AHFlag register(0-7)

copies the flag register at

the top of the stack
PUSHF none PUSHF
FlagStack
Data Transfer Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

copies a word at the top

of the stack to the flag
register POPF
POPF none
StackFlag
Arithmetic Instruction
Arithmetic Instructions These instructions are used to perform
arithmetic operations like addition, subtraction, multiplication, division,
etc.
Arithmetic Instruction
Following is the list of instructions under this group
• Instructions to perform addition
• ADD − Used to add the provided byte to byte/word to word. ADC −
Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction
operation.
Arithmetic Instruction
• Instructions to perform subtraction
• SUB − Used to subtract the byte from byte/word from word.
• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• NPG − Used to negate each bit of the provided byte/word and add
1/2’s complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.
Arithmetic Instruction
• *Instruction to perform multiplication
• MUL − Used to multiply unsigned byte by byte/word by word.
• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.
Arithmetic Instruction
• *Instructions to perform division
• DIV − Used to divide the unsigned word by byte or unsigned double
word by word.
• IDIV − Used to divide the signed word by byte or signed double word
by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign
bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign
bit of the lower word.
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

ADD D, S D=D+S ADD AX, [2050]

ADC D, S D = D + S + prev. carry ADC AX, BX

SUB D, S D=D–S SUB AX, [SI]

SBB D, S D = D – S – prev. carry SBB [2050], 0050

MUL 8-bit register AX = AL * 8-bit reg. MUL BH

MUL 16-bit register DX AX = AX * 16-bit MUL CX

reg.

IMUL 8 or 16 bit register performs signed IMUL CX

multiplication
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE
DIV 8-bit register AX = AX / 8-bit reg. ; AL = DIV BL
quotient ; AH = remainder

DIV 16-bit register DX AX / 16-bit reg. ; AX = DIV CX

quotient ; DX = remainder
IDIV 8 or 16 bit register performs signed division IDIV BL
INC AX
INC D D=D+1 INC [BX] memory
INC[1000] ] direct memory

DEC AL
DEC D D=D–1 DEC [CX] memory
DEC [1000] direct memory
CBW none converts signed byte to CBW
word
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

CWD none converts signed byte to CWD

double word

NEG D D = 2’s compliment of D NEG AL

CMP AX, CX
CMP Mem/Reg1, Mem/Reg1-Mem/Reg1
Mem/Reg1 Subtract two values AX-CXflag [modify]
Never store subtract
result
Arithmetic Instruction
OPCODE OPERAND EXPLANATION EXAMPLE

DAA none decimal adjust DAA

accumulator

ASCII adjust
AAA none accumulator after AAA
addition
ASCII adjust
AAS none accumulator after AAS
subtraction
ASCII adjust
AAM none accumulator after AAM
multiplication
ASCII adjust
AAD none accumulator after AAD
division
Logical Instruction
OPCODE OPERAND DESTINATION EXAMPLE

AND D, S D = D AND S AND AX, 0010

OR D, S D = D OR S OR AX, BX

NOT D D = NOT of D NOT AL

XOR D, S D = D XOR S XOR AL, BL

performs bit-wise AND

TEST D, S operation and affects TEST [0250],
the flag register
Logical Instruction
OPCODE OPERAND DESTINATION EXAMPLE
shifts each bit in D to
SHR D, C the right C times and 0 SHR AL, 04
is stored at MSB
position
shifts each bit in D to
SHL D, C the left C times and 0 is SHL AX, BL
stored at LSB position
ROR D, C rotates all bits in D to ROR BL, CL
the right C times
ROL R, C rotates all bits in D to ROL BX, 06
the left C times
rotates all bits in D to
RCR D, C the right along with RCR BL, CL
carry flag C times
rotates all bits in D to
RCL R, C the left along with RCL BX, 06
carry flag C times
Unconditional Program Execution Transfer Instruction

Opcode Operand Description

CALL address Used to call a procedure and save

their return address to the stack.

RET ---- Used to return from the

procedure to the main program.

Used to jump to the provided

JMP address address to proceed to the next
instruction.

Used to loop a group of

LOOP address instructions until the condition
satisfies, i.e., CX = 0
Conditional Program Execution Transfer Instruction
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential
order.
Following is the list of instructions under this group −
•REP − Used to repeat the given instruction till CX ≠ 0
Eg. REP MOVSB STR1 STR2
It copies byte to byte contents
REP repeats the operation MOVSB until CX becomes zero
•MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
•COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
•INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided
memory location.
•OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
•SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or
string word with a word in AX.
Processor Control Instruction
OPCODE OPERAND EXPLPANATION EXAMPLE
STC none sets carry flag to 1 STC
CLC none resets carry flag to 0 CLC
CMC none compliments the carry CMC
flag
sets directional flag to
STD none 1 STD
resets directional flag
CLD none to 0 CLD

STI none sets the interrupt flag STI

to 1
CLI none resets the interrupt flag CLI
to 0
 Example:
• Determine the effect of each one of the following 8086 instructions:
• i) PUSH [BX]
• ii) DIV DH
• iii) CWD
• iv) MOVSB
• v) MOV START [BX], AL
Assume the following data prior to execution of each one of the above instructions
independently.
[DS]=3000H, [ES]=5000H, [DX]=0400H, [SP]=5000H, [SS]=6000H, [AX]=00A9H, [SI]=0400H,
[DI]=0500H, DF=0, [BX]=6000H, Value of START=05H
[36000H]=02H, [36001]=03H
[50500H]=05H
[30400H]=02H, [30401H]=03H
 Solution:
(i) PUSH [BX]
20 bit physical memory addressed by DS and BX DSx10BX
3000Hx106000H
36000H
20 bit physical memory addressed by SP and SS SSx10SP
6000Hx105000H
65000H
PUSH [BX] pushes 36001H and 36000H into stack locations 64FFFH and 64FFEH respectively.
The SP is decremented by 2 to contain the 20-bit physical address 64FFEH (SS 6000H and SP
4FFEH)
Therefore, [64FFFH] 03H
And [64FFEH] 02H
 Solution:
•   DIV DH
(ii)
Before unsigned division, [DX] 0400H
[DH] 04H
[AX] 00A9H
DIV DH


Quotient, AL2AH
Remainder, AH1H
 Solution:
• (ii) CWD
CWD sign extends AX register into the DX register. Since the sign bit of [AX] 0
After CWD, [DX AX] 000000A9H.
 Solution:
• (iv) MOVSB
MOVSB moves the content of memory addressed by the source [DS] and [SI] to the
destination addressed by [ES] and DI] and then it increments [SI] and DI] by 1 for byte
move.
Since DF0, [DS]=3000H, [SI]=0400H, [ES]=5000H, [DI]=0500H
And the content of physical memory location 30400H is moved to physical memory
50500H.
Since [30400H]=02H, the location 50500H will also contain 02H
Since DF0 after MOVSB, [SI]=0401H, [DI]=0501H
 Solution:
• (v) MOV START [BX], AL
Here, [BX]=6000H, [DS]=3000H, START=05H
The physical memory for the destination
= [DS]x10 [BX]START
=3000Hx106000H05H
=36005H
After MOV START [BX], AL, memory location 36005H will contain A9H