Lecture 4: Continuation of

SystemVerilog
 Last Lecture: Divide by 3 FSM
• Output should be “1” every 3 clock cycles

S2

S0

S1
The double circle indicates the reset state
Slide derived from slides by Harris & Harris from their book 2
 Finite State Machines (FSMs)
• A simple Moore machine looks like the
following
CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

Slide derived from slides by Harris & Harris from their book 3
 FSM Example in SystemVerilog
module divideby3FSM (input logic clk, reset_n,
output logic q);

enum logic [1:0] {S0=2’b00, S1=2’b01, S2=2’b10} state; // declare states as

enum

// next state logic and state register

always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n)
state <= S0;
else begin
case (state)
state transition graph is the same
S0: state <= S1;
thing as a state transition table, which
S1: state <= S2;
S2: state <= S0;
can be specify as a case statement
endcase
end
end

// output logic
assign q = (state == S0); output is “1” every clock cycles when we are in state S0
endmodule

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 FSM Example in SystemVerilog
module divideby3FSM (input logic clk, reset_n,
output logic q);

enum logic [1:0] {S0=2’b00, S1=2’b01, S2=2’b10} state; // declare states as

enum
compiler recognizes this “template” should use
// next state logic and state register positive edge-triggered flip-flops w/ negative edge
always_ff @(posedge clk, negedge reset_n) asynchronous reset should be used.
begin
compiler knows this “if”
if (!reset_n)
state <= S0;
part defines the reset
else begin values for flip-flops.
case (state)
state
S0: state <= S1;
S1: state <= S2; next
output
S2: state <= S0; state FF q
logic
endcase logic
end
end

// output logic
assign q = (state == S0);
endmodule

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 What asynchronous reset means
• “Negative-edge asynchronous reset” means
the following:

reset_n flip-flops get reset on this negedge transition

clk

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 Continuing with the FSM Example
• What if we want to design the “Divide by 3 FSM”
example with just one “always_ff” statement (no
separate “assign” statement)?

• Let’s assume we still want “q” to be “1” when we are

in state “S0”.

• Can we put the logic for “q” instead the “always_ff”

statement?

• Yes, but a flip-flop will be created for “q”!

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 FSM Example in SystemVerilog
module fsm2 (input logic clk, reset_n, output logic q);
enum logic [1:0] {S0=2'b00, S1=2'b01, S2=2'b10} state; // declare states as enum

always_ff @(posedge clk, negedge reset_n)

begin
if (!reset_n) begin
state <= S0; synthesis will generate D-FFs for
q <= 1; both “state” and “q”
end else begin
case (state)
S0: begin
state <= S1;
q <= 0;
end
S1: begin
state <= S2;
q <= 0;
end
S2: begin
state <= S0; in order to have the output “q” = 1 when “state”
q <= 1;
is in S0, have to set the D-FF for “q” in S2 so that
end
the output “q” = 1 when “state” gets to S0.
endcase
end
end
endmodule
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 FSM Example in SystemVerilog
module fsm2 (input logic clk, reset_n, output logic q);
enum logic [1:0] {S0=2'b00, S1=2'b01, S2=2'b10} state; // declare states as enum

always_ff @(posedge clk, negedge reset_n)

begin
if (!reset_n) begin
state <= S0;
compiler knows this “if”
q <= 1; part defines the reset
end else begin values for flip-flops.
case (state)
S0: begin
state <= S1; state
q <= 0; next
end
S1: begin
state FF
state <= S2; logic
q <= 0;
end
S2: begin
state <= S0;
q <= 1; logic for FF q
end “q”
endcase
end
end
endmodule
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 RTL Example
module rtl_example (input logic clk, reset_n, always_ff@(posedge clk, negedge reset_n)
input logic [7:0] a, b, if (!reset_n) begin
output logic [7:0] f, count); count <= 0;
c <= 0; // this c is different than function
// default encoding: s0=2’b00, s1=2’b01, s2=2’b10 state <= s0;
enum logic [1:0] {s0, s1, s2} state; end else begin
logic [7:0] c, t; case (state)
s0: begin
function logic [7:0] myinc(input logic [7:0] x); count <= 0;
logic [7:0] sum; c <= 0;
logic c; // this is an internal c state <= s1;
begin end
c = 1; s1: begin
for (int i = 0; i < 8; i++) begin count <= count + 1;
sum[i] = x[i] ^ c; c <= a + b;
c = c & x[i]; state <= s2;
end end
myinc = sum; s2: begin
end count <= myinc(count);
endfunction c <= a – b;
state <= s0;
always_comb end
begin endcase
t = c << 1; end
f = t + 1;
end endmodule

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 RTL Example
reset_n clk
module rtl_example
clocked always block c logic always block
a 0 00
+ 01 c t
8 f
10 <<1 +1
11 8 8 8
–
b
8
count
0 00
+1 01
10 count
11 8
myinc

s1 00 state
s2 01
10 state
s0 2
11

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 Fibonacci Calculator
• F(0) = 0, F(1) = 1
• F(n) = F(n – 1) + F(n – 2), when n > 1

• Examples:

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 Fibonacci Calculator
• Design a FSM with the interface below.
• input_s is “n”, and fibo_out is “F(n)”.
• Wait in IDLE state until begin_fibo.
• When testbench sees done==1, it will check if fibo_out==
F(input_s).
module fibonacci_calculator (input logic clk, reset_n,
input logic [4:0] input_s,
input logic begin_fibo,
output logic [15:0] fibo_out,
output logic done);
...
always_ff @(posedge clk, negedge reset_n)
begin
... clk
end fibonacci_ fibo_out
reset_n
endmodule input_s calculator
done
begiin_fibo 13
 Fibonacci Calculator
• Basic idea is to introduce 3 registers:
logic [4:0] counter;
logic [15:0] R0, R1;
• Set loop counter to “n”
counter <= input_s;
• Repeat as long as counter is greater than 1 since we
already know what F(0) and F(1) are:
counter <= counter – 1;
R0 <= R0 + R1;
R1 <= R0;
• Finally, set output to “F(n)”
done <= 1;
fibo_out <= R0;

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 Fibonacci Calculator
module fibonacci_calculator (input logic clk, reset_n,
input logic [4:0] input_s,
input logic begin_fibo,
output logic [15:0] fibo_out,
output logic done);
enum logic [1:0] {IDLE=2'b00, COMPUTE=2'b01, DONE=2'b10} state;

logic [4:0] count;

logic [15:0] R0, R1;
COMPUTE:
if (count > 1) begin
always_ff @(posedge clk, negedge reset_n)
count <= count - 1;
begin
R0 <= R0 + R1;
if (!reset_n) begin
R1 <= R0;
state <= IDLE;
end else begin
done <= 0;
state <= DONE;
end else
done <= 1;
case (state)
fibo_out <= R0;
IDLE:
end
if (begin_fibo) begin
count <= input_s;
in clocked always stmts, DONE:
D-FFs keep track of state <= IDLE;
R0 <= 1;
previous value, so the endcase
R1 <= 0;
end
state <= COMPUTE; missing “else” part will
endmodule
end just keep “state” at IDLE.

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 Fibonacci Calculator
• A three state solution is provided.

• Design it using only 2 states (or fewer) w/o creating

flip-flops for fibo_out or done, and should work
for n ≥ 1. Hint: use “assign” statements for
fibo_out and done.

• Use provided “tb_fibonacci_calculator.sv” to verify

your design using ModelSim.

• Synthesize your 2-state “fibonacci_calculator.sv”

design using Quartus.
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 Fibonacci Calculator: 2 States
module fibonacci_calculator (...);

enum logic {IDLE=1'b0, COMPUTE=1'b1} state;

logic [4:0] count;

logic [15:0] R0, R1;

assign done = ...; // no FF will be generated

assign fibo_out = ...; // no FF will be generated

// just update count, R0, R1, state in always_ff

always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n)
...
else case (state)
IDLE:
...
COMPUTE:
...
endcase
end
endmodule

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