Week-3

Module 1
Minimum Mode CPU
Configuration of 8086
Minimum Mode CPU Configuration
Minimum
Mode CPU
Configuration
 Minimum
Mode CPU
Configuration
:
8282
8286
 8286
Transceiver
 •8282 / 8283 Latch:
As shown in the figure, AD0-AD15, A16/S3-A19/S6, and BHE/S7 signals are multiplexed.
These signals are demultiplexed by external latches and ALE signal– generated by the
processor. This is accomplished by using three latch ICs (Intel 8282/8283), two of them
are required for a 16-bit address and three are needed if a full 20-bit address is used.

Explanation: •8286 Trans receiver :

If a system includes several interfaces then to increase current sourcing/sinking
capacities it is necessary to use drivers and receivers (transceiver) for data bus also.
Minimum The Intel 8286 device is used to implement the transceiver block. The 8286 contains 16
tristate elements, eight receivers, and eight drivers. Therefore two 8286s are required

Mode CPU to service 16 data lines of 8086.

•8284 Clock Generator:

Configuration The third component. other than the processor that appears is an 8284 clock

of 8086
generator. The 8284 clock generator does the following functions
1. Clock generation: Crystal oscillator generate clk signal
2. RESET synchronization: RC circuit
3. READY synchronization: Wait State Generator provide ready signal
4. Peripheral clock generation.
Maximum Mode CPU
Configuration of 8086
 Maximum Mode
CPU Configuration
 Maximum Mode
CPU Configuration
of 8086
8288 Bus
Controller
Command Signals
MRDC (Memory Read Command) : It instructs the memory to put the contents of the addressed location on the data bus.
MWTC (Memory Write Command) : It instructs the memory to accept the data on the data bus and load the data into the addressed memory location.
IORC (I/O Read Command) : It instructs an I/O device to put the data contained in the addressed port on the data bus.
IOWC (I/0 Write Command) : It instructs an I/O device to accept the data on the data bus and load the data into the addressed port.
MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls the mode of operation of 8259. It selects cascade operation for 8259 (interrupt
controller) if IOB signal is grounded and enables the I/O bus transceivers if IOB is tied high.
AEN, IOB and CEN  : These pins are used in multiprocessor system. With a single processor in the system, AEN and IOB are grounded and CEN is tied high.
AEN causes the 8288 to enable the memory control signals. IOB (I/O bus mode) signal selects either the I/O bus mode or system bus mode operation. CEN
(control enable) input enables the command output pins on the 8288.
AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write Command) : These signals are similar to IOWC and MWTC except that they are
activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.
 
Differentiate
between
Minimum
and
Maximum
Mode
Bus Timing Diagrams / Machine Cycles of 8086

1. Minimum Mode
( Read / Input and Write / Output
Cycles)
2. Maximum Mode
( Read / Input and Write / Output
cycles)
 Bus Timings for Minimum Mode:
The timing diagrams of input and output transfers for Minimum Mode Configuration of 8086
 • When processor is ready to initiate the bus cycle, it applies a pulse to ALE during T 1. Before the falling edge
of ALE, the address, BHE, M/IO, DEN and DT/R must be stable i.e. DEN = high and DT/R = 0 for input or DT/R
= 1 for output.
• At the trailing edge of ALE, ICs 74LS373 or 8282 latches the address.
• During T2 the address signals are disabled and S3-S7 are available on AD16/S3-AD19/S6 and BHE/S7. Also DEN is
lowered to enable transceiver.
• In case of input operation, RD is activated during T2 and AD0 to AD15 go in high impedance preparing for
input.
Minimum Mode • If memory or I/O interface can perform the transfer immediately; there are no wait states and data is
Read / Write Machine output on the bus during T3.
Cycles: Explanation • After the data is accepted by the processor, RD is raised high at the beginning of T 4.
• Upon detecting this transition during T4, the memory or I/O device will disable its data signals.
• For an output operation, processor applies WR = 0 and then the data on the data bus during T 2.
• In T4, WR is raised high and data signals are disabled.
• For either input or output operation, DEN is raised during T4 to disable the Also M/IO is set according to the
next transfer at this time or during next T1 state. Thus length of bus cycle in 8086 is four clock cycle. If the
bus is to be inactive after completion of bus cycle, then the gap between the successive cycles is filled by
ideal state clock cycles.
• When the memory or I/O device is not able to respond quickly during transfer, wait states (T w) are inserted
between T3 and T4 by disabling the READY input of the 8086. The bus activity during wait state is same as during T 3.
 Bus Timings for
Maximum Mode:
The timing diagrams
of input and output
transfers for Maximum
Mode Configuration of
8086
 • S0,S1,S2 are set at the beginning of bus cycle. On detecting the change
on
passive state S0 = S1 = S2 = 1, the 8288-bus controller will output a
pulse on its ALE and apply a required signal to its DT/R pin during T1.
Minimum Mode
Read / Write Machine • In T2, 8288 will set DEN = 1 thus enabling transceiver. For an input,
Cycles: Explanation 8288 it will activate MRDC or IORC. These signals are activated
until T4.  For an output, the AMWC or AIOWC is activated from T2 to
T4 and MWTC or IOWC is activated from T3 to T4.
• The status bits S0 to S2 remain active until T3 , and become passive
during T3 and T4.
• If ready input is not activated before T3, wait state will be inserted
between T3 and T4.
 Subjective Questions?

1. Differentiate between Minimum mode and Maximum

Mode
2. Draw and explain Minimum Mode CPU configuration.
3. Draw and explain Maximum Mode CPU configuration.
4. Draw and explain read and write machine cycles / Bus
timing diagram of 8086 in Minimum mode and
Maximum mode.
Any Query?