Input Output Organization
Input Output Organization
MUST 2017
Contents
I/O Organization
Input-Output Interface
Asynchronous Data Transfer
Asynchronous Serial Transmission
Modes of Data Transfer
Programmed I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)
I/O Organization
Control
Keyboard
and Printer Magnetic
display disk
terminal
i. Strobe Control
ii. Handshaking
Strobe Signal
Data Bus
Source Destination
Strobe Unit
Unit
Data
Valid data
Strobe
The timing diagram fig. (b) the source unit first places the data on the data bus.
The information on the data bus and strobe signal remain in the active state to
allow the destination unit to receive the data.
Data Transfer Initiated by Destination Unit
Data Bus
Source Destination
Strobe Unit
Unit
Data
Valid data
Strobe
The data must be valid and remain in the bus long enough for the
destination unit to accept it. When accepted the destination unit then
disables the strobe and the source unit removes the data from the bus.
Disadvantage of Strobe Signal
The disadvantage of the strobe method is that, the source unit
initiates the transfer has no way of knowing whether the
destination unit has actually received the data item that was
places in the bus. Similarly, a destination unit that initiates the
transfer has no way of knowing whether the source unit has
actually placed the data on bus. The Handshaking method
solves this problem.
Handshaking
One control line is in the same direction as the data flows in the bus
from the source to destination. It is used by source unit to inform the
destination unit whether there a valid data in the bus. The other control
line is in the other direction from the destination to the source. It is
used by the destination unit to inform the source whether it can accept
the data. The sequence of control during the transfer depends on the
unit that initiates the transfer.
Source Initiated Transfer using Handshaking
The sequence of events shows four possible states that the
system can be at any given time. The source unit initiates
the transfer by placing the data on the bus and enabling
its data valid signal. The data accepted signal is activated
by the destination unit after it accepts the data from the
bus. The source unit then disables its data accepted
signal and the system goes into its initial state.
Handshaking
Data Bus
Destination Unit
Source unit
Ready to accept data.
Place the data on bus. Enable ready for data.
Enable data Valid.
If any of one unit is faulty, the data transfer will not be completed.
Such an error can be detected by means of a Timeout mechanism
which provides an alarm if the data is not completed within time.
Asynchronous Serial Transmission
The transfer of data between two units is serial or
parallel. In parallel data transmission, n bit in the
message must be transmitted through n separate
conductor path. In serial transmission, each bit in the
message is sent in sequence one at a time.
Parallel transmission is faster but it requires many wires.
It is used for short distances and where speed is
important. Serial transmission is slower but is less
expensive.
Asynchronous Serial Transmission
In Asynchronous serial transfer, each bit of message is sent a
sequence at a time, and binary information is transferred only
when it is available. When there is no information to be
transferred, line remains idle.
In this technique each character consists of three points :
i. Start bit
ii. Stop Bit- Last bit, called stop bit is always one and used to
indicate end of characters. Stop bit is always in the 1- state and
frame the end of the characters to signify the idle or wait state.
iii. Character Bit- Bits in between the start bit and the stop bit
are known as character bits. The character bits always follow
the start bit.
Asynchronous Serial Transmission
0 1 1 0 0 0 1 0 1
Start Stop
bit Character bits bits
The transmitter register accepts a data byte from CPU through the
data bus and transferred to a shift register for serial transmission.
The receive portion receives information into another shift register, and
when a complete data byte is received it is transferred to receiver
register.
CPU can select the receiver register to read the byte through the data
bus. Data in the status register is used for input and output flags.
First In First Out Buffer (FIFO)
i. Programmed I/O
Status Error
Busy
Ready
CPU reads word from I/O module & writes it to memory or
CPU reads word from memory & writes it to I/O module
Is
transfer
NO complete
yes
Execute next instruction
Drawback of the Programmed I/O
The main drawback of the Program Initiated I/O was that the
CPU has to monitor the units all the times when the program is
executing. Thus the CPU stays in a program loop until the I/O
unit indicates that it is ready for data transfer. This is a time
consuming process and the CPU time is wasted a lot in
keeping an eye to the executing of program.
Status Error
Ready
Is
transfer
NO complete
yes
Execute next instruction
Direct Memory Access (DMA)
In the Direct Memory Access (DMA) the interface transfer the data
into and out of the memory unit through the memory bus. The
transfer of data between a fast storage device such as magnetic disk
and memory is often limited by the speed of the CPU. Removing
the CPU from the path and letting the peripheral device manage the
memory buses directly would improve the speed of transfer. This
transfer technique is called Direct Memory Access (DMA).
Direct Memory Access (DMA)
Bus Grant BG
WR Write
i. DMA Burst
i. Address Register