Semiconductor Memory

ECE213

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 Introduction
• There are two types of memories that are used in digital systems:
Random-access memory(RAM): perform both the write and read operations.

Read-only memory(ROM): perform only the read operation.

• The read-only memory is a programmable logic device. Other

such units are the programmable logic array(PLA), the
programmable array logic(PAL), and the field-programmable gate
array(FPGA).

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 Random-Access Memory
• A memory unit stores binary information in groups of bits called words.
1 byte = 8 bits
1 word = 2 bytes (or more)
• The communication between a memory and its environment is achieved through data input
and output lines, address selection lines, and control lines that specify the direction of
transfer.

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 Content of a memory
• Each word in memory is assigned
an identification number, called an Memory content

address, starting from 0 up to 2k-1,

where k is the number of address
lines.
• The number of words in a memory
with one of the letters K=210,
M=220, or G=230.
64K = 216 2M = 221 4G = 232

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 Write and Read operations
• Transferring a new word to be stored into memory:
1. Apply the binary address of the desired word to the
address lines.
2. Apply the data bits that must be stored in memory
to the data input lines.
3. Activate the write input.
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 Write and Read operations
• Transferring a stored word out of memory:
1. Apply the binary address of the desired word to the address lines.
2. Activate the read input.
• Commercial memory sometimes provide the two control inputs for reading
and writing in a somewhat different configuration.

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 Types of memories
• In random-access memory, the word locations may be
thought of as being separated in space, with each word
occupying one particular location.
• In sequential-access memory, the information stored in
some medium is not immediately accessible, but is
available only certain intervals of time. A magnetic disk
or tape unit is of this type.
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 Types of memories
• In a random-access memory, the access time is always
the same regardless of the particular location of the
word.
• In a sequential-access memory, the time it takes to
access a word depends on the position of the word with
respect to the reading head position; therefore, the
access time is variable.
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 Static RAM
• SRAM consists essentially of internal latches that store the
binary information.
• The stored information remains valid as long as power is
applied to the unit.
• SRAM is easier to use and has shorter read and write cycles.
• Low density, low capacity, high cost, high speed, high power
consumption.
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 Dynamic RAM
• DRAM stores the binary information in the form of electric
charges on capacitors.
• The capacitors are provided inside the chip by MOS transistors.
• The capacitors tends to discharge with time and must be
periodically recharged by refreshing the dynamic memory.

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 Dynamic RAM
• DRAM offers reduced power consumption and larger storage
capacity in a single memory chip.
• High density, high capacity, low cost, low speed, low power
consumption.

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 Types of memories
• Memory units that lose stored information when power
is turned off are said to be volatile.
• Both static and dynamic, are of this category since the
binary cells need external power to maintain the stored
information.
• Nonvolatile memory, such as magnetic disk, ROM, retains
its stored information after removal of power.
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 Memory decoding
• The equivalent logic of a binary cell that stores one bit of information is
shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

SR latch with NOR gates

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 4X4 RAM
• There is a need for decoding circuits to select
the memory word specified by the input
address.
• During the read operation, the four bits of
the selected word go through OR gates to
the output terminals.
• During the write operation, the data
available in the input lines are transferred
into the four binary cells of the selected
word.
• A memory with 2k words of n bits per word requires k address lines that go into kx2 k decoder.

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 Coincident decoding
address
• A decoder with k inputs and 2k
outputs requires 2k AND gates with
k inputs per gate.
• Two decoding in a two-dimensional
selection scheme can reduce the
number of inputs per gate.
• 1K-word memory, instead of using a
single 10X1024 decoder, we use
two 5X32 decoders.

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 Address multiplexing
• DRAMs typically have four times the density of SRAM.

• The cost per bit of DRAM storage is three to four times less than
SRAM. Another factor is lower power requirement.

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 Address multiplexing
• Address multiplexing will reduce the number of pins in the IC
package.

• In a two-dimensional array, the address is applied in two parts at

different times, with the row address first and the column address
second. Since the same set of pins is used for both parts of the
address, so can decrease the size of package significantly.

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 Read-Only Memory
• A block diagram of a ROM is shown below. It consists of k address
inputs and n data outputs.
• The number of words in a ROM is determined from the fact that k
address input lines are needed to specify 2k words.

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 Construction of ROM
• Each output of the decoder represents a memory address.
• Each OR gate must be considered as having 32 inputs.
• A 2k X n ROM will have an internal k X 2k decoder and n OR gates.

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 Truth table of ROM
• A programmable connection between two lines is logically equivalent to a
switch that can be altered to either be close or open.
• Intersection between two lines is sometimes called a cross-point.

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 Programming the ROM
In Table, 0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

1 0 1 1 0 0 1 0

X : means connection

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 Combinational circuit implementation
• The internal operation of a ROM can be interpreted in two way: First, a
memory unit that contains a fixed pattern of stored words. Second,
implements a combinational circuit.
• Previous figure may be considered as a combinational circuit with eight
outputs, each being a function of the five input variables.

A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29)

Sum of minterms

In Table, output A7

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 Example
• Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the square of the input number.
Derive truth table first

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 Example

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 Types of ROMs
• The required paths in a ROM may be programmed in four
different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse /fuse intact
3. Erasable PROM or EPROM: placed under a special ultraviolet light
for a given period of time will erase the pattern in ROM.
4. Electrically-erasable PROM(EEPROM): erased with an electrical
signal instead of ultraviolet light.

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 Combinational PLDs
• A combinational PLD is an integrated circuit with
programmable gates divided into an AND array and an OR
array to provide an AND-OR sum of product implementation.
• PROM: fixed AND array constructed as a decoder and
programmable OR array.
• PAL: programmable AND array and fixed OR array.
• PLA: both the AND and OR arrays can be programmed.

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 Combinational PLDs

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 Programmable Logic Array
• The decoder in PROM example can be replaced by an array of
AND gates that can be programmed to generate any product term
of the input variables.
• The product terms are then connected to OR gates to provide the
sum of products for the required Boolean functions.
• The output is inverted when the XOR input is connected to 1
(since x⊕1 = x’). The output doesn’t change and connect to 0
(since x⊕0 = x).

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 F1 = AB’+AC+A’BC’
PLA
F2 = (AC+BC)’

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 Programming Table
1. First: list the product terms numerically
2. Second: specifiy the required paths between inputs and
AND gates
3. Third: specify the paths between the AND and OR gates
4. For each output variable, we may have a T(ture) or
C(complement) for programming the XOR gate

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 Simplification of PLA
• Careful investigation must be undertaken in order to
reduce the number of distinct product terms, PLA has a
finite number of AND gates.
• Both the true and complement of each function should
be simplified to see which one can be expressed with
fewer product terms and which one provides product
terms that are common to other functions.
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 Example
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = ∑(0, 1, 2, 4)
F2(A, B, C) = ∑(0, 5, 6, 7)
The two functions are simplified in the maps shown.
We will take different terms.

1 elements
0 elements

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 PLA table by simplifying the function

• Both the true and complement of

the functions are simplified in sum
of products.
• We can find the same terms from
the group terms of the functions of
F1, F1’,F2 and F2’ which will make the
minimum terms.

F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

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 PLA implementation

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 Programmable Array Logic
• The PAL is a programmable logic device with a fixed OR array and a programmable
AND array.

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 PAL
• When designing with a PAL, the Boolean functions must be
simplified to fit into each section.
• Unlike the PLA, a product term cannot be shared among two
or more OR gates. Therefore, each function can be simplified
by itself without regard to common product terms.
• The output terminals are sometimes driven by three-state
buffers or inverters.

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 Example
w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean functions:

w = ABC’ + A’B’CD’
x = A + BCD
y = A’B + CD + B’D’
z = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D

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 PAL Table
• z has four product terms, and we can replace by w with two product terms,
this will reduce the number of terms for z from four to three.

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 PAL implementation

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 Fuse map for example

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 Field Programmable Gate Array
(FPGA)

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 Evolution of implementation technologies
• Logic gates (1950s-60s) trend toward
higher levels
• Regular structures for two-level logic (1960s-70s)
of integration
– muxes and decoders, PLAs
• Programmable sum-of-products arrays (1970s-80s)
– PLDs, complex PLDs
• Programmable gate arrays (1980s-90s)
– densities high enough to permit entirely new
class of application, e.g., prototyping, emulation,
acceleration

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 Gate Array Technology (IBM - 1970s)
• Simple logic gates
– combine transistors to
implement combinational
and sequential logic
• Interconnect
– wires to connect inputs and
outputs to logic blocks
• I/O blocks
– special blocks at periphery
for external connections
• Add wires to make connections
– done when chip is fabbed
• “mask-programmable”
– construct any circuit

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 Field-Programmable Gate Arrays
• Logic blocks
– to implement combinational
and sequential logic
• Interconnect
– wires to connect inputs and
outputs to logic blocks
• I/O blocks
– special logic blocks at periphery
of device for external connections

• Key questions:
– how to make logic blocks programmable?
– how to connect the wires?
– after the chip has been fabbed

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 CPLD vs. FPGA
• CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-
products logic arrays feeding a relatively small number of clocked registers.
• Results in less flexibility, with the advantage of more predictable timing delays and a higher
logic-to-interconnect ratio.
• The FPGA architectures are dominated by interconnect. This makes them far more flexible (in
terms of the range of designs that are practical for implementation within them) but also far
more complex to design for.
• In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually
much larger in terms of resources than CPLDs.
• Typically only FPGA's contain more advanced embedded functions such as adders, multipliers,
memory and other hardened functions.
• Another common distinction is that CPLDs contain embedded flash to store their configuration
while FPGAs usually, but not always, require an external flash

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 Programmability of FPGAs
• User programmability of CPLDs and FPGAs is achieved via
user-programmable switch technologies.
• For CPLDs, floating-gate transistors are used like EPROM
or EEPROM. On the otherhand, FPGAs normally use
SRAM (static RAM) or antifuse technology.
• Properties of the switches, such as, size, on-resistance, and
capacitance dictate trade-offs in architecture.
• In SRAM based FPGAs, there is an SRAM bit
corresponding to each of the programmable points within
the device.
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• When the device is powered-on or reset, it reads a configuration
program from an off-chip memory and loads it into on-chip SRAM.
• The configuration program defines the logic function realized by
individual logic blocks and interconnections.
• Devices using SRAM based switching can be reprogrammed easily
by just changing the configuration program.
• FPGAs belonging to Xilinx, Plassey, Algotronix, Concurrent Logic,
Toshiba, etc. are SRAM based.
• SRAM provides fast reprogrammability at the cost of large area (at
least five transistors for cell and one for switch).

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 SRAM controlled switching

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 Floating gate programming

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 Comparison between programming techniques

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 FPGA Logic Blocks
• There are wide variations in the logic block structure of
FPGAs available from different vendors.
• They vary in number of inputs and outputs, amount of
area consumed, complexity of logic functions that they
can realize, total number of transistors needed, and so
on.
• The logic blocks can broadly be classified into the
following two categories – Fine Grain, Coarse Grain
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