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Chapter 4 Cache Memory

William Stallings, Computer Organization and Architecture, 9 th Edition
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Objectives

 How are internal memory elements of a computer structured?

 After studying this chapter, you should be able to:
 Present an overview of the main characteristics of computer
memory systems and the use of a memory hierarchy.
 Describe the basic concepts and intent of cache memory.
Discuss the key elements of cache design.
 Distinguish among direct mapping, associative mapping, and
set-associative mapping.
 Explain the reasons for using multiple levels of cache.
 Understand the performance implications of multiple levels of
memory.
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Contents

4.1- Computer Memory Systems Overview

4.2- Cache Memory Principles
4.3- Elements of Cache Design
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4.1- Computer Memory System
Overview

 Characteristics of Memory System.

 The Memory Hierarchy
Key Characteristics of Computer Memory Systems
+ Characteristics of Memory Systems

 Location
 Refers to whether memory is internal and external to the computer
 Internal memory is often equated (make equal) with main memory
 Processor requires its own local memory, in the form of registers
 Cache is another form of internal memory
 External memory consists of peripheral storage devices that are accessible
to the processor via I/O controllers

 Capacity
 Memory is typically expressed in terms of bytes

 Unit of transfer
 For internal memory the unit of transfer is equal to the number of electrical
lines into and out of the memory module
Method of Accessing Units of Data
Sequential Direct Random
Associative
access access access

Each addressable location in

A word is retrieved based on
Memory is organized into Involves a shared read-write memory has a unique,
a portion of its contents
units of data called records mechanism physically wired-in
rather than its address
addressing mechanism

Each location has its own

The time to access a given
Individual blocks or records addressing mechanism and
Access must be made in a location is independent of
have a unique address based retrieval time is constant
specific linear sequence the sequence of prior
on physical location independent of location or
accesses and is constant
prior access patterns

Any location can be selected

Cache memories may
Access time is variable Access time is variable at random and directly
employ associative access
addressed and accessed

Main memory and some

More details: Next slides cache systems are random

access
Method of Accessing Units of Data:
Direct Access
Location of each sector is idenfified
by a unique number

T1: seek time, time for moving

the head to the accessed track
T2: Rotational delay, time for
rotating the disk to position the
head to the beginning of the
accessed sector
T3: Transfer time, time for
rotating the disk to access all the
accessed sector
Each sector is accessed using
Access time = T1 + T2 + T3
different access time
Method of Accessing Units of Data:
Random Access

CPU Address bus Mem.

Decoder

The time to access a given location is independent

of the sequence of prior accesses and is constant

Main memory
Capacity and Performance:

The two most important characteristics of memory

Three performance parameters are used:

Memory cycle time

Access time (latency) • Access time plus any additional time
Transfer rate
• For random-access memory it is the time required before second access can • The rate at which data can be transferred
it takes to perform a read or write commence into or out of a memory unit
operation • Additional time may be required for • For random-access memory it is equal to
• For non-random-access memory it is the transients to die out on signal lines or to 1/(cycle time)
time it takes to position the read-write regenerate data if they are read
mechanism at the desired location destructively
• Concerned with the system bus, not the
processor
+ Memory
 The most common forms are:
 Semiconductor memory
 Magnetic surface memory
 Optical
 Magneto-optical

 Several physical characteristics of data storage are important:

 Volatile memory
 Information decays naturally or is lost when electrical power is switched off
 Nonvolatile memory
 Once recorded, information remains without deterioration until deliberately changed
 No electrical power is needed to retain information
 Magnetic-surface memories : Are nonvolatile
 Semiconductor memory : May be either volatile or nonvolatile
 Nonerasable memory
 Cannot be altered, except by destroying the storage unit
 Semiconductor memory of this type is known as read-only memory (ROM)

 For random-access memory the organization is a key design issue

 Organization refers to the physical arrangement of bits to form words
+ Memory Hierarchy
 Design
constraints on a computer’s memory can be
summed up by three questions:
 How much, how fast, how expensive

 There is a trade-off among capacity, access time, and cost

 Faster access time, greater cost per bit
 Greater capacity, smaller cost per bit
 Greater capacity, slower access time

 Theway out of the memory dilemma is not to rely on a

single memory component or technology, but to employ a
memory hierarchy

A great capacity memory but cheap and low speed + one or some small capacity
memory but fast and more expensive (cache) .
+ Memory Hierarchy…
+
4.2- Cache Memory Principles

 What is cache?
 Cache and Main Memory
 What is a Cache? Memory Management
Unit - MMU

Cache: A small
size, expensive,
memory which
has high-speed
access is located
between CPU
and RAM (large
memory size,
cheaper, and
lower-speed
Memory).
L0: cache in CPU, working with
CPU rate. It is not usually
implemented.
Cache/Main Memory Structure
Main memory is
divided into the
same size blocks.
Some blocks will
be loaded to
cache.

Each line Address in cache

includes a tag is different from
that identifies those in main
which particular memory  A
block is mapping is
currently being needed.
stored
Cache Addr  Main Mem Addr
 4.3- Elements of Cache Design

Overview of
cache design
parameters
Main Memory Address Specifications
Opcode Memory Add.
(1) Physical Address
(2) Abtract Address
(3) Virtual Address 3010 3005

App
Physical Addresses
3005

CPU
PC=3010 3000
Mem. Of
Operating
Mem. System
3005
Decoder
Main Memory Address Specifications
Physical Addresses

3005
When the operating system is
upgraded, the OS needs more
Old
memory ( ex: 4000 bytes), old
App.
applications are not compatible.
4000
Address must be specified by an
other way to ensure that old 3005
programs can be run in new OS. Mem. Of
 Abstract addresses Operating
System
Main Memory Address Specifications
Abstract Addresses
All addresses in an application will be
specified by compilers using an offset 5
(difference) from the base address 4005
(position at which the app. is loaded) pp.
- A register (base register) must be
added to maintain the base address of 4000
the process
 An address is specified by <base,
offset) Mem. Of
Operating
CPU System
Base:4000
Mem.
5
+ Add. bus Decoder
 Main Memory Address Specifications
Virtual Addresses: Paging- Segmentation
Contemporary OSs allows many X=10
programs running concurrently 4
although system’s memory is limited. 3
Solution is that the program content
and memory will be divided into
some pages (same-size, ex: 4KB) or
segments (different size). Only 2
needed pages/segments are loaded to
system memory. Address of X:
Compilers must translate (3,4)
1
program’s addresses to a suitable
form (virtual address). Virtual
address format:
0
<page/segment, offset>
Main Memory Address Specifications
Virtual Addresses: Paging- Segmentation
- When an instruction/data is
accessed, physical address
must be supplied. A
mapping is needed as a
mean for determining
physical addresses from
their virtual addresses. This
mapping is implemented in
OS as a page table.
- A hardware is needed to
translate virtual address to
physical address MMU –
Memory Management Unit.
Operating Systems - Tannenbaum
Main Memory Address Specifications
Virtual Addresses: Paging- Segmentation

Time-sharing
mechanism

- How do OSs permit many program running concurrently? 

Only some pages/segments of a process are loaded and the time-
sharing mechanism is applied.
- Advantages of memory paging: Many apps can run concurrently
in limited memory. A page of a program can loaded into arbitrary
physical memory location.
- Disadvantages of memory paging: If a page fault occurs, cost
must be paid when an in-memory frame must be swapped to disk
from memory (swap out) then a page from disk will be loaded to
memory (swap in) – Paging replacement.
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Cache Addresses: Virtual Address
 Virtual memory
 Facility that allows programs to address memory from a
logical point of view, without regard to the amount of main
memory physically available. Only some needed small parts
of a program are loaded to main memory at a time. So, a
large program can run although memory size is smaller
 When used, the address fields of machine instructions
contain virtual addresses
 For reads from and writes to main memory, a hardware
memory management unit (MMU) translates each virtual
address into a physical address in main memory
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Logical
and Virtual/Logical cache stores
data using virtual addresses

Physical
Caches
Physical cache stores data
using physical addresses
Mapping Function
 Because there are fewer cache lines than main memory blocks, an
algorithm is needed for mapping main memory blocks into cache
lines

 Three techniques can be used:

Direct Associative Set Associative

• The simplest technique • Permits each main memory • A compromise that exhibits the
• Maps each block of main block to be loaded into any line strengths of both the direct and
memory into only one possible of the cache associative approaches while
cache line • The cache control logic reducing their disadvantages
interprets a memory address
simply as a Tag and a Word
field
• To determine whether a block
is in the cache, the cache
control logic must
simultaneously examine every
line’s Tag for a match
+ Direct
Mapping
The block j in main
memory will be loaded
to the line i of the
cache: i = j mod m

A block in main
memory can be
load to any line of
the cache
 Direct Mapping Cache Organization
READ BY
s: Block index YOURSELF
r: Line index
w: word index

penalty
 READ BY
YOURSELF
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Direct

Mapping

Example
 READ BY
YOURSELF
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Direct Mapping Summary
 Address length = (s + w) bits
 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory = 2s+ w/2w = 2s
 Number of lines in cache = m = 2r
 Size of tag = (s – r) bits
 READ BY
YOURSELF
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Victim Cache

 Originally proposed as an approach to reduce the conflict misses of

direct mapped caches without affecting its fast access time

 Fully associative cache

 Typical size is 4 to 16 cache lines

 Residing between direct mapped L1 cache and the next level of

memory
 READ BY
YOURSELF
Fully Associative Cache Organization
A block
can be
loaded to
any cache
line

Compare to
each Tag
 READ BY
YOURSELF
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Associative

Mapping

Example
 READ BY
YOURSELF
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Associative Mapping Summary

 Address length = (s + w) bits

 Number of addressable units = 2s+w words or bytes
 Block size = line size = 2w words or bytes
 Number of blocks in main memory= 2s+ w/2w = 2s
 Number of lines in cache = undetermined
 Size of tag = s bits
 READ BY
YOURSELF
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Set Associative Mapping

 Compromise (thỏa hiệp) that exhibits the strengths of both

the direct and associative approaches while reducing their
disadvantages
 Cache consists of a number of sets Go to Replacement
Algorithms
 Each set contains a number of lines
 A given block maps to any line in a given set
 e.g. 2 lines per set
 2 way associative mapping
 A given block can be in one of 2 lines in only one set
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Mapping From Main

Memory
to Cache:

k-Way
Set Associative
READ BY
YOURSELF
 READ BY
k-Way YOURSELF
Set
Associative
Cache
Organization
 READ BY
YOURSELF
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Set Associative Mapping Summary

 Address length = (s + w) bits

 Number of addressable units = 2s+w words or bytes

 Block size = line size = 2w words or bytes

 Number of blocks in main memory = 2s+w/2w=2s

 Number of lines in set = k

 Number of sets = v = 2d

 Number of lines in cache = m=kv = k * 2 d

 Size of cache = k * 2d+wwords or bytes

 Size of tag = (s – d) bits

READ BY
YOURSELF
 READ BY
YOURSELF
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Varying Associativity Over Cache Size
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Replacement Algorithms
 Two situations:
 Cache hit: Accessed address exists in cache
 Cache miss: Accessed address does not exist in cache. The memory block
containing it must be loaded to the cache

 Oncethe cache has been filled, when a new block is brought into the
cache, one of the existing blocks must be replaced
 Fordirect mapping there is only one possible line for any particular
block and no choice is possible
 Forthe associative and set-associative techniques a replacement
algorithm is needed
 Toachieve high speed, an algorithm must be implemented in
hardware
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The four most common replacement
algorithms are:
 Least recently used (LRU) 2 bits in tag can be used: 00, 01, 10, 11. Line with
 Most effective 00 should be swap out. See the note.
 Replace that block in the set that has been in the cache longest with no
reference to it
 Because of its simplicity of implementation, LRU is the most popular
replacement algorithm

 First-in-first-out (FIFO)
 Replace that block in the set that has been in the cache longest
 Easily implemented as a round-robin or circular buffer technique

 Least frequently used (LFU)

 Replace that block in the set that has experienced the fewest references
 Could be implemented by associating a counter with each line
 Write Policy
When a block that is resident in the
There are two problems to contend
cache is to be replaced there are two
with:
cases to consider:

If the old block in the cache has not been altered

More than one device may have access to main
then it may be overwritten with a new block
memory
without first writing out the old block

If at least one write operation has been A more complex problem occurs when
performed on a word in that line of the cache multiple processors are attached to the same
then main memory must be updated by writing bus and each processor has its own local cache
the line of cache out to the block of memory - if a word is altered in one cache it could
before bringing in the new block conceivably invalidate a word in other caches
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Write Through
and Write Back
 Write through- Ghi thẳng
 Simplest technique
 All write operations are made to main memory as well as to the cache
 The main disadvantage of this technique is that it generates substantial (heavy)
memory traffic and may create a bottleneck

 Write back-Ghi ngầm

 Minimizes memory writes
 Updates are made only in the cache
 Portions of main memory are invalid and hence accesses by I/O modules
can be allowed only through the cache
 This makes for complex circuitry and a potential bottleneck
 Line Size

When a block of data

is retrieved and Two specific effects come
placed in the cache into play:
not only the desired As the block size • Larger blocks reduce the number
word but also some increases more useful of blocks that fit into a cache
• As a block becomes larger each
number of adjacent data are brought into additional word is farther from
words are retrieved the cache the requested word

As the block size The hit ratio will

increases the hit ratio begin to decrease as
will at first increase the block becomes
because of the bigger and the
principle of locality probability of using
the newly fetched
information becomes
Larger line size  More data  Cache less than the
probability of reusing
hit increases, but expensive and more the information that
has to be replaced
data in cache but not used (Normal: 64-
128 bytes)
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Multilevel Caches
 As logic density has increased it has become possible to have a cache on the same
chip as the processor

 The on-chip cache reduces the processor’s external bus activity and speeds up
execution time and increases overall system performance
 When the requested instruction or data is found in the on-chip cache, the bus access is
eliminated
 On-chip cache accesses will complete appreciably faster than would even zero-wait state
bus cycles
 During this period the bus is free to support other transfers

 Two-level cache:
 Internal cache designated as level 1 (L1)
 External cache designated as level 2 (L2)

 Potential savings due to the use of an L2 cache depends on the hit rates in both the
L1 and L2 caches

 The use of multilevel caches complicates all of the design issues related to caches,
including size, replacement algorithm, and write policy
Hit Ratio (L1 & L2) For 8 Kbyte and 16Kbyte L1
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Unified Versus Split Caches
 Has become common to split cache:
 One dedicated to instructions
 One dedicated to data
 Both exist at the same level, typically as two L1 caches

 Advantages of unified cache: Higher hit rate

 Balances load of instruction and data fetches automatically
 Only one cache needs to be designed and implemented

 Trend is toward split caches at the L1 and unified caches for higher
levels

 Advantages of split cache:

 Eliminates cache contention (tranh chấp) between instruction fetch/decode
unit and execution unit
 Important in pipelining (cơ chế đường ống, output của xử lý này là input
của xử lý kế tiếp)
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Exercises
 4.1- What are the differences among sequential access, direct access, and
random access?

 4.2-What is the general relationship among access time, memory cost,

and capacity?

 4.3- How does the principle of locality relate to the use of multiple
memory levels?

 4.4- What are the differences among direct mapping and associative
mapping,?

 4.5- For a direct-mapped cache, a main memory address is viewed as

consisting of three fields. List and define the three fields.

 4.6- For an associative cache, a main memory address is viewed as

consisting of two fields. List and define the two fields.
+ Summary Cache
Memory
Chapter 4

 Characteristics of Memory  Elements of cache design

Systems  Cache addresses
 Location
 Cache size
 Capacity
 Mapping function
 Unit of transfer
 Replacement algorithms
 Memory Hierarchy  Write policy
 How much?  Line size
 Number of caches
 How fast?
 How expensive?
 Cache memory principles