8086 Hardware Specifications

Dept. of Computer Science and Engineering

BRAC University
CSE 341 Team
Lecture References:

 Book:

 Microprocessors and Interfacing: Programming and Hardware,

Author: Douglas V. Hall

 The 8086/8088 Family: Design, Programming, And Interfacing,

Author: John Uffenbeck.

CSE – 341: Microprocessors

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8086 Pin Specification
 is a 40-pin DIPs; Dual in-line package
 DIP refers to a rectangular housing with two parallel rows of electrical
connection pins.
 DIPs have a notch on one end to show its correct orientation.
 The pins are then numbered as shown in the figure below.

CSE – 341: Microprocessors

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8086 Pin Diagram
 
Recap
• 8086 is a 16-bit microprocessor.
• Meaning it has 16 data lines/bus.
• It has 20 address lines/bus.
• Each memory location holds only 1 byte
• Can address different memory locations
• It could address up to 1MB of memory.

min mode

max mode

CSE – 341: Microprocessors

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8086 Pin Specification

 
CLK
• provides basic timing to control processor operation
• frequencies of different versions are 5, 8 or10 MHz
• asymmetric with a 33% duty cycle

CSE – 341: Microprocessors

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8086 Pin Specification

 
• lines are multiplexed bidirectional address/data bus.
• During they carry 16-bit address.
• In remaining clock cycles , 16-bit data.
• carry lower order data byte
• carry higher order data byte

CSE – 341: Microprocessors

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8086 Pin Specification

 
• lines are multiplexed address and status bus.
• During they carry the highest order 4-bit address.
• D, status signals.
• , segment identifiers as in table below

S4 S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access

CSE – 341: Microprocessors

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8086 Pin Specification

 
: Indicates if interrupt is enabled or disabled.
• If =1 , then the IF = 1, so the interrupt is enabled.
• If =0 , then the IF = 0, so the interrupt is disabled.

: Indicates if 8086 is the bus master or not

• If = 0 , 8086 is the bus master
• If = 1 , 8086 is not the bus master

CSE – 341: Microprocessors

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8086 Pin Specification

 
• Bus High Enable
• is active low
• To indicate the transfer of data over
• Related to memory bank
• Selects odd/high memory bank when is 0
• : Reserved for further development

CSE – 341: Microprocessors

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8086 Pin Specification

 
• is active low
• Indicates read operation when low
• Processor reading from memory or I/O device
• Is low during states of the read cycle

CSE – 341: Microprocessors

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8086 Pin Specification

 
• Is examined by the WAIT instruction.
• If this pin is Low, execution continues.
• Else the processor waits in an idle state.

CSE – 341: Microprocessors

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8086 Pin Specification

 
READY
• acknowledgement from a slow I/O device or memory
• To indicate ready/completion of data transfer
• When low, microprocessor enters wait state, .

CSE – 341: Microprocessors

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8086 Pin Specification

 
RESET
• To reset the system reset.
• And terminates the current activity.
• Must be active for at least four clock cycles

CSE – 341: Microprocessors

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8086 Pin Specification

 
INTR
• Interrupt request
• Used to request a hardware interrupt.
• Can be masked.

 
N
• Non-maskable interrupt signal.
• Causes a type-2 interrupt. 
• Initiates the interrupt at the end of the current
instruction.

CSE – 341: Microprocessors

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8086 Pin Specification
 
• 8086 works in two modes:
• Minimum Mode if high
• Maximum Mode if low
• Functions of pins 24-31 depend on the mode
• Minimum Mode - single processor
• Maximum Mode - multi processor

min mode

max mode

CSE – 341: Microprocessors

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Minimum Mode Pin Specification

 
HOLD
• To request for bus by another device.
• It is an active HIGH signal.

 
• Hold Acknowledgment.
• When acknowledged, it relinquish the bus to the
requesting device

CSE – 341: Microprocessors

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Minimum Mode Pin Specification

 
• Active low write signal.
• Writes data to memory or output device depending on
signal.

 
• Differentiates memory access from I/O access.
• When high, memory is accessed.
• When low, I/O devices are accessed.

CSE – 341: Microprocessors

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Minimum Mode Pin Specification

• Data Transmit/Receive signal.

• indicates the direction of flow through the
transceiver.
• When high, data is transmitted out i.e. written to.
• When low, data is received in i.e. read in.

• Data Enable signal.

• Used to enable a transceiver connected to the P

CSE – 341: Microprocessors

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Minimum Mode Pin Specification

 
• Address Latch Enable
• indicates an address is available on bus
• active high during state

CSE – 341: Microprocessors

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Minimum Mode Pin Specification

• An active low signal.

• An interrupt acknowledge signal.
• When microprocessor receives an INTR signal, it
acknowledges the interrupt by generating this signal
• When low it indicates an interrupt is being serviced.

CSE – 341: Microprocessors

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8086 Maximum Mode Pins
Dept. of Computer Science and Engineering
BRAC University
CSE 341 Team
Maximum Mode Pin Specification
 

• Instruction queue status.

• Instruction queue is 6 bytes long
Function
0 0 No Operation. During the last clock cycle,
nothing was
taken from the queue.
0 1 First Byte. The byte taken from the queue was
the first byte of the instruction.
1 0 Queue Empty. The queue has been
reinitialized as a result
of the execution of a transfer instruction.
1 1 Fetch subsequent byteSubsequent Byte. The
byte taken from the queue was a subsequent
byte of the instruction.

CSE – 341: Microprocessors

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Maximum Mode Pin Specification
 

• Status Signals.
• indicate operation done by the microprocessor
• Related to memory and I/O access control signals.
Function
0 0 0 Interrupt acknowledgement
0 0 1 Read data from I/O port
0 1 0 Write data from I/O port
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive state
CSE – 341: Microprocessors
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Maximum Mode Pin Specification

•  When low, all interrupts are masked

• Indicates to other processors to not request for system
bus.
• No HOLD request is granted.
• No bus is relinquished to the other processors

CSE – 341: Microprocessors

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Maximum Mode Pin Specification

• Request/Grant pins.
• Other processors request the CPU through these for
system bus.
• CPU sends acknowledge signal on the same lines.
• .

CSE – 341: Microprocessors

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QUIZ
  
1) Assuming you want to type a secret message using a keypad

connected to an 8086 microprocessor, deduce the values of the

following pins during that time. Justify your anwers too.

a) e.g. mention if low (0) / high (1) and why.

b)

2) Do you think there may be other pins involved? If so, justify

your answer.

CSE – 341: Microprocessors

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8086 Clocks & Timing Diagrams
Dept. of Computer Science and Engineering
BRAC University
CSE 341 Team
Microprocessor Operation

Fetch Decode

Execute

 An instruction e.g. MOV [7531h], AX ; SUB CH, [0ABCh] etc

 The time a µP requires to complete fetch-(decode)-execute
operation of a single instruction is known as Instruction Cycle
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Microprocessor Operation
 Instruction Cycle consists of one or more Machine Cycles
 A basic µP operation such as reading/writing a byte from or
to memory or I/O port is called a Machine/Bus cycle

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Microprocessor Operation
 A Machine (bus) cycle consists of at least four clock cycles,
called T states.
 One cycle of a clock is called a State
 Each read or write operation takes 1 bus cycle.

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Clock Generation
 Clock generator circuit is 8284A and connected to pin 19
(CLK) of 8086.

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 System Clock Concept
• 8086 is found to operate in between 5 to 10 Mhz.
𝑇
  𝑜𝑓𝑓 𝑇
  𝑜𝑛
• An 8086 running at 5MHz, its clock pulses will be
of 200ns and it would take 800ns for a complete
bus cycle.

For a 10MHz 8086, its clock pulses will be of

100ns and it would take 400ns for a complete
bus cycle.
CSE – 341: Microprocessors
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 Clock States - Why are there T states?

   In 8086, address and data lines are multiplexed to reduce number of pins e.g.
else 32 pins would have been needed instead of 16
 The µp needs time to change the signals during each bus cycle.
 Memory devices need time to interpret the address value and then read/write
the data (access time)
 A specific defined action occurs during each T state (T1 - T4)
 T1 : Address is output
 T2 : Bus cycle type (Mem/IO, read/write)

 T3: Data is supplied / Data is received

 T4 : Data latched by CPU, control signals removed

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READ BUS Timing (Complete BUS Cycle)
T1: Address is output

Address of memory is sent out by 8086 via address bus

Used Control signals: ALE, DT/R’, M/IO’ shows some output
CSE – 341: Microprocessors
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READ BUS Timing (Complete BUS Cycle)
T2: Bus cycle type (MEMORY/IO, READ/WRITE)

8086 issues either RD’ or WR’ and DEN’

In case of WRITE (WR) operation, data to be written appear on data bus
CSE – 341: Microprocessors
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READ BUS Timing (Complete BUS Cycle)
T3: Data is supplied

READY is sampled at the end of T2

If READY is low, T3 becomes a wait state (Tw), means no operation (NOP).
In READ bus cycle data bus is sampled at end of T3
CSE – 341: Microprocessors
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READ BUS Timing (Complete BUS Cycle)
T4: Data latched by µP, control signals removed

All bus signals deactivated in preparation for next bus cycle

µP sampled data bus for data that read from M or I/O
CSE – 341: Microprocessors
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Clock States
 A specific, defined action occurs during each T states (T1 – T4)

 T1: Address is output

 Address of memory is sent out by 8086 via address bus
 Used Control signals: ALE, DT/R’, M/IO’ shows some output

 T2: Bus cycle type (MEMORY/IO, READ/WRITE)

 8086 issues either RD’ or WR’ and DEN’
 In case of WRITE (WR) operation, data to be written appear on data
bus

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Clock States
 T3: Data is supplied
 READY is sampled at the end of T2
 If READY is low, T3 becomes a wait state (Tw), means no operation (NOP).

 In READ bus cycle data bus is sampled at end of T3

 T4: Data latched by µP, control signals removed

 All bus signals deactivated in preparation for next bus cycle
 µP sampled data bus for data that read from M or I/O
 At trailing edge of WR’, transfer data to M or I/O

CSE – 341: Microprocessors

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 8086 Ready pin
 The READY input is controlled to insert “Wait states” into the timing of
the microprocessor for slower memory and I/O components..
 If the READY pin is at a logic 0 level, the micro-processor enters into
wait states and remains idle.
 When it is high (logic 1), it indicates that the device is ready to transfer
data.
 A wait state is a situation in which a computer processor is waiting for
the completion of some event before resuming activity.
 A program or process in a wait state is inactive for the duration of the
wait state.
CSE – 341: Microprocessors
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Ready pin and Wait state
 When a computer processor works at a faster clock speed  than the random

access memory ( RAM ) that sends it instructions, it is set to go into a wait

state for one or more clock cycles so that it is synchronized with RAM

speed. In general, the more time a processor spends in wait states, the

slower the performance of that processor.

 Wait states are a pure waste for a processor's performance. Modern designs

try to eliminate or hide them using a variety of techniques: CPU caches, 

instruction pipelines, instruction prefetch, simultaneous multithreading and

others.
CSE – 341: Microprocessors
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Thank You
Questions are welcome in the discussion class

CSE – 341: Microprocessors

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