TEST BENCHES

TEST BENCHES
 VHDL – COMBINATIONAL
entity halfsub is
Port ( a,b : in STD_LOGIC; diff,barr : out STD_LOGIC);
end halfsub;
architecture ahalf of halfsub is
component ex_or2
port (a,b: in std_logic; c: out std_logic);
end component;
component and12
port (a,b : in std_logic; c: out std_logic);
end component; CONTI…
component not2
port (a: in std_logic; b: out std_logic);
end component;
signal s: std_logic;
begin
g1 : ex_or2 port map(a,b,diff);
g2 : not2 port map (a,s);
g3 : and12 port map (s,b,barr);
end ahalf;
CONTI…
 ex_or2 - COMPONENT
entity ex_or2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ex_or2;

architecture Behavioral of ex_or2 is

begin
c<= a xor b;
end Behavioral;
 not2 - COMPONENT
entity not2 is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end not2;

architecture Behavioral of not2 is

begin
b<= not a;
end Behavioral;
 and12 - COMPONENT
entity and12 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and12;

architecture Behavioral of and12 is

begin
c<= a and b;
end Behavioral;
 TEST BENCH – HALF SUBRACTOR
entity atest is begin
end atest; x1: ex_or2 port map (w,x,y);
x2: and12 port map (s,x,z);
x3: not2 port map (w,s);
architecture btest of atest is
p1:process
component ex_or2
begin
port (a,b : in std_logic;
w<='0'; x<='0';
c: out std_logic);
wait for 5ns;
end component;
w<='0';x<='1';
component and12
wait for 10ns;
port (a,b : in std_logic;
w<='1';x<='0';
c: out std_logic);
wait for 15ns;
end component;
w<='1';x<='1';
component not2
wait for 20ns;
port (a : in std_logic;
end process p1;
b: out std_logic);
end btest;
 VHDL –- SEQUENTIAL
VHDL SEQUENTIAL
entity dff is if (reset = '1') then
Port ( d : in STD_LOGIC; a:='0';
clock: in STD_LOGIC; elsif (clock'event and clock
reset :in STD_LOGIC; = '1') then
q : out STD_LOGIC; a:=d;
qb : out STD_LOGIC ); end if;
end dff; q<=a;
architecture Be of dff is qb<= not a;
begin end process;
process (clock,reset,d) end Be;
variable a: std_logic;
begin
 TEST BENCH – D:FF
entity tb_dff is x1: dff1 port map
end tb_dff; (d1,clk,r1,q1,qb1);
p1:process
begin
architecture Behavioral of
tb_dff is r1<='0'; wait for 40ns;
component dff1 d1<='0';clk<='0'; wait for 10ns;
port (d,clock,reset : in d1<='0';clk<='1'; wait for 10ns;
std_logic; d1<='1';clk<='0'; wait for 10ns;
q,qb: out std_logic); d1<='1';clk<='1'; wait for 10ns;
end component; end process p1;
signal d1,clk,r1,q1,qb1 : end Behavioral;
std_logic;
begin
 Verilog –– COMBINATIONAL
VERILOG combinational
module andgate(a, b, y);
input a;
input b;
output y;

assign y = a & b;
endmodule
 TEST BENCH – AND GATE
module andgate_tb(); t_a = 1'b0;
wire t_y; t_b = 1'b1;
reg t_a,t_b; #5
t_a = 1'b1;
andgate my_gate ( .a(t_a), t_b = 1'b0;
.b(t_b), .y(t_y)); #5
t_a = 1'b1;
t_b = 1'b1;
initial
#100 $finish;
begin
end
$monitor(t_a,t_b,t_y);
t_a = 1'b0;
t_b = 1'b0; endmodule
#5
 FULL ADDER - PRGM WITH WIRE
module fulladder(a, and (x,a,b);
b,c, sum, carry); and (y,b,c);
input a; and (z,c,a);
input b,c; or (carry,a,b,c);
output sum; endmodule
output carry;
wire x,y,z;
xor (sum,a,b,c);
 TEST BENCH FOR FULL ADDER -
PRGM WITH WIRE
module fulladder_tb(); c1 = 1'b1;
wire sum1,carry1; #20
reg a1,b1,c1; a1 = 1'b1;
fulladder my_gate ( .a(a1), .b(b1), .c(c1), b1 = 1'b0;
.sum(sum1), .carry(carry1)); c1 = 1'b0;
initial #20
begin a1 = 1'b1;
$monitor(a1,b1,c1,sum1,carry1); b1 = 1'b0;
a1 = 1'b0; c1 = 1'b1;
b1 = 1'b0; #20
c1 = 1'b0; a1 = 1'b1;
#20 b1 = 1'b1;
a1 = 1'b0; c1 = 1'b0;
b1 = 1'b0; #20
c1 = 1'b1; a1 = 1'b1;
#20 b1 = 1'b1;
a1 = 1'b0; c1 = 1'b1;
b1 = 1'b1; #100 $finish;
c1 = 1'b0; end
 VERILOG – SEQUENTIAL
module counter(clk, count);
input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule
VERILOG – SEQUENTIAL – TEST BENCH
module counter_tb();
reg clk;
wire[3:0] count;
counter my_counter ( .clk(clk), .count( count ) );
initial
Begin
clk = 0;
#200 $finish;
end
always
begin
#2 clk = ~clk;
end
always @( posedge clk)
$display("Count = %b", count );
endmodule
 VHDL
SYNTHESIS
 VHDL
LANGUAGE
BASICS
 VHDL – DESIGN UNITS
Five kinds of design units.

• Entity declaration.
• Architecture body.
• Configuration declaration.
• Package declaration.
• Package body.
 DATA OBJECTS

• A data object holds a value or a sequence of

values of a certain type.
 FOUR CLASSES OF DATA OBJECTS
• Constant.

• Variable.

• Signal.

• File.
 DATA TYPES

• A data types represents a collection of values.

 AVAILABLE DATA TYPES

• Enumeration type.
• Integer type.
• Physical type.
• Floating point type.
• Array type.
• Record type.
• Access type.
• File type.
• Sub type.
 DESIGN DESCRIPTION
• A design is described using one or more
concurrent statements in an architecture
body.

• The execution of a concurrent statement is

based on events on the signal in its input list,
and thus the order of concurrent statements
within an architecture body is not important.
 CONCURRENT STATEMENTS
• Block statement.
• Concurrent procedure call statement.
• Concurrent assertion statement.
• Concurrent signal assignment statement.
• Component instantiation statement.
• Generate statement.
• Process statement.
 PROCESS STATEMENT

• A process statement is used to describe the

behavior of a design using sequential
statements.

• These statements execute sequentially.

 SEQUENTIAL STATEMENTS
• Wait statement.
• Report statement.
• Assertion statement.
• Signal assignment statement.
• Variable assignment statement.
• Procedure call statement.
• If statement.
• Case statement.
CONTI…
 SEQUENTIAL STATEMENTS
• Loop statement.
• Next statement.
• Exit statement.
• Return statement.
• Null statement.
 SYNTHESIS

• WHAT IS SYNTHESIS?

Synthesis is the process of constructing a

gate level netlist from a model of a circuit
described in VHDL.
 PROCESS OF SYNTHESIS
VHDL MODEL

TARGET Synthesis AREA AND

TECHNOLOGY TIMING CONSTRAINTS
RTL module
builder

UN OPTIMIZED LOGIC OPTIMIZER

GATE LEVEL NETLIST
OPTIMIZED GATE LEVEL NETLIST
 A SYNTHESIS PROGRAM

• Generate a RTL netlist, which is comprised of

register transfer level blocks such as flip-flops,
arithmetic-logic-units, and multiplexers,
interconnected by wires.
SAME BEHAVIOR, DIFFERENT STYLES
STYLEAA
STYLE

STYLE
STYLE B
B

CIRCUIT
(MODELS)

STYLE
STYLEDD
STYLE C
STYLE C
 SAME BAHAVIOR, DIFFERENT STYLES

• Since there is no direct object in VHDL that

means a latch or a flip-flop, each synthesis
system may provide different mechanisms to
model a flipflop or a latch.
• Each synthesis system therefore defines its
own subset of VHDL language including its
own personalized modeling style.
 MODELING
HARDWARE
ELEMENTS FOR
SYNTHESIS
 MODELING A WIRE
• A wire can be modeled using a signal.

• A variable can also be used to model a wire.

• However, multiple assignments to the same

variable are considered as different instances
of a wire.
 A SIGNAL BECOMES A WIRE
entity mux2x1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sel : in STD_LOGIC;
ena : in STD_LOGIC;
zq : out STD_LOGIC);
end mux2x1;
architecture sig_wires of mux2x1 is
signal tra, trb, tor: std_logic;
begin
tra <= a and sel;
trb <= b and (not sel);
tor <= tra or trb;
zq <= tor when ena = '1' else 'Z';
end sig_wires;
 DESIGN STATISTICS FROM
SYNTHESIS REPORT
• Design Statistics
• # IOs :5

• Cell Usage :
• # BELS :2
• # INV :1
• # LUT3 :1
• # IO Buffers :5
• # IBUF :4
• # OBUFT :1
RTL SCHEMATIC
 A VARIABLE AS WIRE
entity mux2x1 is begin
Port ( a : in STD_LOGIC; tra := a and sel;
b : in STD_LOGIC; trb := b and (not sel);
sel : in STD_LOGIC; tor := tra or trb;
ena : in STD_LOGIC;
zq : out STD_LOGIC); if ena = '1' then
end mux2x1; zq <= tra;
else
architecture var_wires of zq <= 'Z';
mux2x1 is end if;
begin end process;
process (a,b,sel,ena) end var_wires;
variable
 DESIGN STATISTICS FROM
SYNTHESIS REPORT
• Design Statistics
• # IOs :5

• Cell Usage :
• # BELS :2
• # INV :1
• # LUT2 :1
• # IO Buffers :4
• # IBUF :3
• # OBUFT :1
RTL – SCHEMATIC
 REFER TEXT BOOK FOR THE REMAINING
TOPICS
• Modeling combinational logic.
• Modeling sequential logic.
• Modeling a flipflop.
• Flipflop with asynchronous preset and clear.
• Flipflop with synchronous preset and clear.
• Modeling a latch.
 VERILOG
SYNTHESIS
 LOGIC SYNTHESIS
• What is logic synthesis?
Logic synthesis is the process of converting a high-level
description of design into an optimized gate-level
representation.
Logic synthesis uses a standard cell library which have
simple cells, such as basic logic gates like and, or, and nor, or
macro cells, such as adder, muxes, memory, and flip-flops.
Standard cells put together are called technology library.
Normally the technology library is known by the transistor
size (0.18u, 90nm).
TYPICAL DESIGN FLOW
CONTRUCTS NOT SUPPORTED IN SYNTHESIS
CONSTRUCTS SUPPORTS IN SYNTHESIS
CONTRUCTS SUPPORTS IN SYNTHESIS
 COMBINATIONAL CIRCUIT MODELING
USING ASSIGN

• Combinational circuits modeling in Verilog can

be done using assign and always blocks.
 EX – TRI STATE BUFFER
module tri_buf (a,b,enable);
input a;
output b;
input enable;
wire a,enable;
wire b;
assign b = (enable) ? a : 1'bz;
endmodule
EX – TRI STATE BUFFER
 EX – MUX
module mux_21 (a,b,sel,y);
input a, b;
output y;
input sel;
wire y;
assign y = (sel) ? b : a;
endmodule
EX – MUX
 COMBINATIONAL CIRCUIT MODELING
USING ALWAYS
• While modeling using always statements,
there is the chance of getting a latch after
synthesis if care is not taken. (No one seems
to like latches in design, though they are
faster, and take lesser transistor. This is due to
the fact that timing analysis tools always have
problems with latches; glitch at enable pin of
latch is another problem).
 COMBINATIONAL CIRCUIT MODELING
USING ALWAYS
• One simple way to eliminate the latch with
always statement is to always drive 0 to the
LHS variable in the beginning of always code
as shown in the code below.
 3:8 DECODER USING ALWAYS
module decoder_always (in,out);
input [2:0] in;
output [7:0] out;
reg [7:0] out;
always @ (in)
begin
out = 0;
case (in)
3'b001 : out = 8'b0000_0001;
3'b010 : out = 8'b0000_0010;
3'b011 : out = 8'b0000_0100;
3'b100 : out = 8'b0000_1000;
3'b101 : out = 8'b0001_0000;
3'b110 : out = 8'b0100_0000;
3'b111 : out = 8'b1000_0000;
endcase
end
endmodule
Modeling a combinational logic using assign
stmt
Modeling a combinational logic using always
stmt
COMBINATIONAL LOGIC
• // Using a reg • wire c;
• // ----------------------------- • and (c,a,b); // output is always
• wire a,b; first in the list
• reg c; • // using a built in primitive (with
instance name)
• always @ (a or b)
• // -----------------------------
• c = a & b;
• reg a,b;
• // Using a wire
• wire c;
• // -----------------------------
• and u1 (c,a,b); // output is always
• wire a,b,c; first in the list
• assign c = a & b; • // if c is an output
• // using a built in primitive • // -----------------------------
(without instance name)
• output c;
• // -----------------------------
• reg a,b;
• reg a,b;
• assign c = a & b;
MULTIPLEXER USING PROCEDURE
• // 1. using an always
• always@(a or b or sel)
• if (sel == 1’b1)
• c = a;
• else
• c = b;
 USING TERNARY OPERATOR
• // 2. using the ternary operator
• wire c = sel ? a : b;
 USING CASE STATEMENT
• // 3. using the case statement
• always @ (a or b or sel)
• case (sel)
• 1’b1: c = a;
• 1’b0: c = b;
• endcase
 PRIOTITY DECODER CASE STATEMENT

• // 1. using a case statement

• always @ (sl or a or b or c)
• case (sel)
• 2’b11: d = a;
• 2’b10: d = b;
• default: d = c;
• endcase
 PRIORITY DECODER USING IF/ELSE STMT

• // 2. using an if statement
• always @ (sl or a or b or c)
• if (sel == 2’b11)
• d = a;
• else if (sel ==2’b10)
• d = b;
• else
• d = c;
 PARALLEL PRIORITY DECODERS USING
SYNTHESIS DIRECTIVE
• // using a synthesis directive
• always @ (sl or a or b or c)
• case (sel) // parallel_case
• 2’b11: d = a;
• 2’b10: d = b;
• default:d = c;
• endcase
 D TYPE FLIPFLOP
• // 1. positive edge triggered D flip flop
• always @ (posedge clock)
• q <= d;
• // 2. negative edge triggered D flip flop
• always @ (negedge clock)
• q <= d;
 RESETTABLE D TYPE FLIPFLOPS
• // 1. synchronously resettable D flip flop
• always @ (posedge clock)
• if (reset)
• q <= 1’b0;
• else
• q <= d;
• // 2. asynchronously resettable D flip flop
• // (active high async reset)
• always @ (posedge clock or posedge reset)
• if (reset)
• q <= 1’b0;
• else
• q <= d;
• // 3. asynchronously resettable D flip flop
• // (active low reset)
• always @ (posedge clock or negedge reset)
• if (~reset)
• q <= 1’b0;
• else
• q <= d;
DATA ENABLED AND CLOCK GATED FLIPFLOPS

• // 1. data enabled flip flop

• always @ (posedge clock)
• if (enable)
• q <= d;
• // 2. D flip flop with gated clock
• wire gclk = (clock && enable);
• always @ (posedge gclk)
• q <= d;
 LATCHES
• // 1. latch
• always @ (enable or d)
• if (enable)
• q = d;
• // 2.resettable latch
• always @ (enable or d or reset)
• if (reset)
• q = 1’b0;
• else if (enable)
• q = d;
SEQUENTIAL CIRCUIT MODELING

• Sequential logic circuits are modeled using

edge sensitive elements in the sensitive list of
always blocks.
• Sequential logic can be modeled only using
always blocks.
• Normally we use nonblocking assignments for
sequential circuits.
 SIMPLE FLIP FLOP
module flif_flop (clk,reset, q, d);
input clk, reset, d;
output q;
reg q;
always @ (posedge clk )
begin
if (reset == 1)
begin
q <= 0;
end
else
begin
q <= d;
end
end
endmodule