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VLSI Design of Radix-4 Signed-Digit Encoding Based Pre-Encoded Multipliers

The document proposes a pre-encoded multiplier design using Non-Redundant radix-4 Signed-Digit (NR4SD) encoding to reduce the number of partial products by half. It stores the pre-encoded coefficients in a memory using 2 bits per coefficient. This reduces the area and power consumption compared to conventional and pre-encoded Modified Booth multiplier designs. Simulation and synthesis results show that the proposed NR4SD multipliers achieve higher performance with reduced area and power.

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surya pratap
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56 views

VLSI Design of Radix-4 Signed-Digit Encoding Based Pre-Encoded Multipliers

The document proposes a pre-encoded multiplier design using Non-Redundant radix-4 Signed-Digit (NR4SD) encoding to reduce the number of partial products by half. It stores the pre-encoded coefficients in a memory using 2 bits per coefficient. This reduces the area and power consumption compared to conventional and pre-encoded Modified Booth multiplier designs. Simulation and synthesis results show that the proposed NR4SD multipliers achieve higher performance with reduced area and power.

Uploaded by

surya pratap
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VLSI Design of Radix-4 Signed-Digit Encoding

based Pre-
Encoded Multipliers
Abstract
• Introducing architecture of pre-encoded multipliers
based on off-line encoding of coefficients.

• To this extend, the Non-Redundant radix-4 Signed-Digit


(NR4SD) encoding technique.

• Uses the digit values {− 1 , 0 , +1 , +2} or {− 2 , − 1 , 0 , +1},


is proposed leading to a multiplier design.

• Using less complex partial products implementation.


Introduction

 Speed of multiplication operation is of great importance in


processors today.
 Past multiplication was generally implemented via a
sequence of addition, subtraction, and shift operations.
 Multiplication can be considered as a series of repeated
additions.
 Each step of addition generates a partial product.
 Most computers, the operand usually contains the same number
of bits.
Existing System

Conventional 1-digit BCD FA


4-bit binary adder at the beginning to add the two BCD
digits and a Carry-input.

Overflow detection(two AND gates and a 3-input OR


gate).

Another 4-bit binary adder which adds


0110-overflow logic is ‘High’
0000-overflow logic is ‘Low’.

This is the correction stage.


Modified Booth Encoder

•To achieve high-speed multiplication, multiplication


algorithms using parallel counters
•Used for longer operands.
•computation time is proportional to the logarithm of the
word length of operands
1. To reduce the number of partial products by half, by
using the technique of radix-4 Booth recoding.
2. Instead of shifting and adding for every column of the
multiplier term and multiplying by 1 or 0, we only take
every second column, and multiply by ±1, ±2, or 0, to
obtain the same results.
NON-REDUNDANT RADIX-4 SIGNED
DIGIT ALGORITHM

NR4SD - Encoding Scheme at the (a) Digit


and (b) Word Level.
NR4SD + Encoding Scheme at the (a) Digit
and (b) Word Level.
Proposed Block Diagram

System Architecture of the NR4SD Multipliers.


•partial products is reduced to half.
•Two bits stored in ROM: n2j+1, n+2j for the NR4SD- or
n+2j+1, n2j for the NR4SD+form.
•Reduce the memory requirement to +1 bits per
coefficient.
•pre-encoded NR4SD multipliers need extra hardware to
generate the signals for the NR4SD and NR4SD+ form.
Applications

 Multimedia and communication systems,


 Real-time signal processing like

audio signal processing,


video/image processing, or large-capacity data
processing
Advantages

 Reduced area

 Reduced Power
 Reduced Delay
 High Performance
Tools used

• Modelsim: The written HDL code is simulated by using this


tool for checking the functionality of code.
• Xilinx: The simulated code is then synthesized on this tool
and hardware is generated by the based on written code.
Simulation result of Pre-encoded Multiplier
Synthesis Results of RTL schematic
Synthesis Results of Technology schematic
Timing Report:
CONCLUSION:

pre-encoded multipliers are explored by off-line encoding


the standard coefficients and storing them in system memory.
The proposed pre-encoded NR4SD multiplier designs are
more area and power efficient compared to the conventional
and pre-encoded MB designs.
Gains of the proposed pre-encoded NR4SD multipliers in
terms of area complexity and power consumption
THANK YOU

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