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Module 5 Session 1

The document discusses interrupts and interfacing applications for the 8051 microcontroller. It covers the basics of interrupts, including interrupt service routines (ISR), polling vs interrupts, and the steps in executing an interrupt. It also describes the 8051 interrupt registers - IE (Interrupt Enable), IP (Interrupt Priority), and TCON (Timer Control). The 8051 has 5 interrupt sources - reset, timer 0 overflow, timer 1 overflow, external hardware 0, and external hardware 1. The IP register controls interrupt priority and the programmer can alter the default priorities of timer interrupts.

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88 views

Module 5 Session 1

The document discusses interrupts and interfacing applications for the 8051 microcontroller. It covers the basics of interrupts, including interrupt service routines (ISR), polling vs interrupts, and the steps in executing an interrupt. It also describes the 8051 interrupt registers - IE (Interrupt Enable), IP (Interrupt Priority), and TCON (Timer Control). The 8051 has 5 interrupt sources - reset, timer 0 overflow, timer 1 overflow, external hardware 0, and external hardware 1. The IP register controls interrupt priority and the programmer can alter the default priorities of timer interrupts.

Uploaded by

SOMESH
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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MICROCONTROLLER (18EC46)

MODULE 5:
8051 Interrupts and Interfacing Applications

SESSION 1:
Basics of Interrupts & 8051 Interrupt Registers
Module Syllabus
1. 8051 Interrupts:
i. 8051 Assembly language programming to generate an external interrupt using
a switch
ii. 8051 C programming to generate a square waveform on a port pin using a
Timer interrupt.
2. 8051 Assembly language interfacing programming
i. ADC-0804
ii. DAC
iii. LCD
iv. Stepper motor
Interrupts of Basics

When multiple devices are connected to a microcontroller/microprocessor, the devices are


serviced in two ways:
1. Polling
2. Interrupts
Polling vs Interrupts
POLLING INTERRUPTS
CPU constantly checks whether the device The devices requiring services, alerts the CPU
needs attention
Software based approach to service the Hardware based approach to service the
devices devices
CPU services the devices The interrupt handler services the devices
CPU checks the device at regular interval The device can interrupt the CPU at any time
CPU time is wasted by repeatedly checking CPU is interrupted by the device only once
the device
Devices cannot be prioritised Devices can be prioritised
Devices cannot be masked Devices can be masked
Interrupt Service Routine
Interrupt Service Routine(ISR):

 Also called the interrupt handler

 It is a software program that is executed when a device sends an interrupt request to


CPU.

 After the execution of ISR, the normal execution of the main program is executed.

Every interrupt has an exclusive ISR.

For every interrupt, there is a fixed location in memory that holds the address its ISR.

The group of memory locations where the addresses of ISRs is stored is called interrupt
vector table.
Steps in executing an interrupt
Steps in executing an interrupt
1) The microcontroller finishes the instruction it is executing and saves the address of the next instruction
(PC) on the stack.

2) The microcontroller saves the current status of all the interrupts internally (i.e., not on the stack).

3) The microcontroller jumps to interrupt vector table that holds the address of the ISR .

4) The microcontroller gets the address of the ISR from the interrupt vector table and starts to execute the
ISR until it reaches the last instruction of the subroutine, which is RETI (return from interrupt).

5) Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted.
First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack
into the PC. Then it starts to execute from that address.
8051 Interrupts
1. Reset
2. Timer 0 overflow interrupt- ET0
3. Timer 1 overflow interrupt- ET1
4. External hardware interrupt- EX0
5. External hardware interrupt- EX1
6. Serial communication interrupt- RI/TI
Interrupt Priority Interrupt ISR Address
Reset 00h
0 External hardware interrupt- EX0 03h
1 Timer 0 overflow interrupt- ET0 0Bh
2 External hardware interrupt- EX1 13h
3 Timer 1 overflow interrupt- ET1 1Bh
4 Serial communication interrupt- RI/TI 23h
8051 Interrupt Registers
1. IE (Interrupt Enable) Register
2. IP (Interrupt Priority) Register
3. TCON( Timer Control) Register
IE (Interrupt Enable) Register
Bit addressable register responsible for enabling and disabling the interrupt
IP (Interrupt Priority) Register
 The register is used to interrupt priority (IP).
 A low priority interrupt can be interrupted by an high priority interrupt, but not
interrupted by another low priority interrupt.
 If two interrupts of different priority levels are received simultaneously, the request of
higher priority level is served.
 If the requests of the same priority levels are received simultaneously, then the internal
polling sequence determines which request is to be serviced.
IP (Interrupt Priority) Register
 By default ET0 is of priority value 1 (which is the highest) and ET1 is of priority value 3
(which is lower than ET0).
 The programmer can alter this priority.
 If  IP.0 is set to ‘0’ and then IP.2 is set to ‘0’ – then the priority order changes.
 ET1 will change to priority value 1
 ET0 will change to priority value 3
TCON( Timer Control) Register
TCON specifies the type of external interrupt to the 8051 microcontroller .
The two external interrupts, can be either edge or level triggered, based on the values of
appropriate bits in the register.
THANK YOU

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