Chapter 3: Introduction to

Assembly Language Programming

CEG2400 - Microcomputer Systems

Ceg2400 Ch3 assembly V.6b 1

 Objective
• In this lecture, you will learn some basic
assembly language operations for ARM7

• In the laboratory session, we will use the

microprocessor programmed with the
assembly language.

The assembly architecture for Intel / ARM is different

You will learn the detail in CSCI3420
Ceg2400 Ch3 assembly V.6b 2
 Overview
1. General introduction
2. Introduction to Assembly Language Programming
3. Study the Current Program Status Register (CPSR)
– N (negative) bit
– Z (zero) bit
– C (carry) bit
– V (overflow) bit
4. Study the Data processing operations
– Arithmetic operations (add subtract etc)
– Logical operations (and, or etc)
– Register MOVes (mov etc)
– Comparison Operations (cmp etc)

Ceg2400 Ch3 assembly V.6b 3

 What is assembly language?
• Very low level, the code that CPU understands
• Very close to machine code
• Every C++ / Pascal code can be translates to
assembly
High level
languages C+ High level
+ ,Pascal
Assembly code
Machine code Low level
Hardware

Ceg2400 Ch3 assembly V.6b 4

 1) General introduction –
of ARM Features
• Load-Store architecture
– Load (from memory to Central processing Unit CPU
registers)
– Store (from CPU registers to memory)
• Fixed-length (32-bit) instructions
– Each machine instruction is 32-bit, no more no
less.
• Conditional execution of ALL instructions
– The condition register (CPSR) holds the result
condition: the result is +ve, -Ve, overflow, etc
Ceg2400 Ch3 assembly V.6b 5
 Registers 暫存器

• Registers in a CPU store temporary data in the

processor
– Transfers to/from memory (i.e. Load/Store) are
relatively slow
– Operations involving registers only are fast

Ceg2400 Ch3 assembly V.6b 6

ARM Registers in the ARM CPU
32-bit

This shaded part is not

studied at the moment

Stack Reg.
Link Reg.
Program counter

Ceg2400 Ch3 assembly V.6b 7

Important registers at the moment
Register 32-bit wide/ usage
name
R0-R12 General purpose registers

R14 Link register

(For calling subroutine)
R15 Program counter (PC)

Ceg2400 Ch3 assembly V.6b 8

 2) Introduction to assembly language
programming
• The following is a simple example which illustrates some of the core
constituents of an ARM assembler module:

operands
label opcode The objects to be operate by opcode comment
9
Ceg2400 Ch3 assembly V.6b
 Assemble Instruction
• One line of code - first : ADD r1,r2,r3

optional

opcode

Label Operand Operand Operand

(optional) 1 2 3
Ceg2400 Ch3 assembly V.6b 10
 General purpose register R0-R12 usage
• MOV r0,#15 Put Data=15
Into the box (R0)
• Opcode : MOV Operands : r0,#15
• In C++, you may write “int a= 15;” R0
• Meaning : MOVe the value #15 (decimal) into register
R0.
– “MOV” means “to move”
– R0 is register 0 (32-bit)
– # (hash) means it is an intermediate value, defined by a
number following #.
– If you add ‘0x’ as suffix, the number is in hexadecimal
Code : In register:
Ceg2400 Ch3 assembly V.6b 11
 Branch function (BL) is an instruction in
ARM
• BL = branch and link

• When a subroutine (function) is needed to be

called, BL is required.
• It will run the instruction in another address
first, and return to the address in link register
afterwards.

Ceg2400 Ch3 assembly V.6b 12

 Branch function (BL) is an instruction in
ARM
• Example:
BL firstfunc ; In C++, you may write Firstfunc();
this instruction means
–Content in R14 (link register) is replaced with
content of R15(program counter=PC)+4.
–Content of PC is replaced by the address of
firstfunc

Ceg2400 Ch3 assembly V.6b 13

 Exercise 3.1
What is the function of Firstfun, and what is the address of
Firstfunc? Fill in the shaded areas.
Address (H) Comments Before instruction is run After instruction is run
PC• start All registers are rest to 0 here R14=link R0 R1 R14=link R0 R1
R15=PC R15=PC
0000 0000 MOV r0,#15 ;Set up parameter

MOV r1,#20 ;Set up parameter

BL Firstfunc ;Branch, call

subroutine
Firstfunc
SW1 Meaning stop here : Software interrupt (will be discussed alter)
Firstf ;subroutine
unc
ADD r0,r0,r1 ;Add r0+r1r0

MOV pc, lr Return from

subroutine, to
caller
end ;end of file

Ceg2400 Ch3 assembly V.6b 14

Current Program Status Register (CPSR)

contains conditional flags and other status bits

Ceg2400 Ch3 assembly V.6b 15

 ARM Programmer's
Model (con't)
 R0 to R12 are general purpose registers (32-bits)
 R13 stack pointer, R14 link register, CPSR (may call it R16)
 Used by programmer for (almost) any purpose without restriction
 R15 is the Program Counter (PC)
 In p.6, the remaining shaded ones are system mode registers - used
during interrupts, exceptions or system programming (to be
considered in later lectures)
 Current Program Status Register (CPSR) contains conditional flags
and other status bits

Ceg2400 Ch3 assembly V.6b 16

 ARM’s CPSR flags
From http://infocenter.arm.com/help/topic/com.arm.doc.dui0068b/DUI0068.pdf

• The ALU status flags

• The CPSR contains the following ALU status flags:
• N Set when the result of the operation was Negative.
• Z Set when the result of the operation was Zero.
• C Set when the operation resulted in a Carry.
• V Set when the operation caused an overflow.
– C flag: A carry occurs if the result of an addition is greater than or
equal to 232, if the result of a subtraction is positive, or as the result
of an inline barrel shifter operation in a move or logical instruction.
– V flag: Overflow occurs if the result of an add, subtract, or compare
is greater than or equal to 231, or less than –231.

Ceg2400 Ch3 assembly V.6b 17

 Condition codes
• In order to do conditional branches and other instructions, some
operations implicitly set flags
– Note: no need to use subtraction because in 2’s complement all operations can be
treated as addition. Adding a positive number to a negative number is subtraction.
• Question
– Give examples of arithmetic operations which will cause
N,Z,C,V to be set to 1

• N = 1 if MSB of (r1 - r2) is '1‘ (MSB of result is sign bit, 1 = negative)

• Z=1 when the result is zero
• C=1 when a binary addition generates a carry out; (for 32-bit integer 2’s
complement addition, C is ignored, see appendix.)
• V=1 (when result of add, subtract, or compare is >= 231, or < –231.). I.e.
• if two -ve numbers are added, the result is +ve (underflow), then V=1.
• if two +ve numbers are added, the result is -ve (overflow), then V=1
• If the two numbers are of different signs, no over/underflow, then V=0.

Ceg2400 Ch3 assembly V.6b 18

 Overflow and Underflow will set V=1
http://www.khmerson.com/~eia213/binnum.ppt
http://en.wikipedia.org/wiki/Integer_(computer_science)
• Overflow
– When two +ve numbers are added (MSB is 0) , the result is
–ve (MSB is 1)
• Underflow
– When two -ve numbers are added (MSB is 1) , the result is
+ve (MSB is 0)
• Note:
– If two numbers have different signs, no
overflow/underflow will occur.
– MSB is the most significant bit
– IN 2’s compliment representation MSB is the sign bit (see
appendix)
Ceg2400 Ch3 assembly V.6b 19
 Overflow and Underflow
http://www.khmerson.com/~eia213/binnum.ppt
Convert hex to decimal : http://easycalculation.com/hex-converter.php
http://en.wikipedia.org/wiki/Integer_(computer_science)
• Overflow :When two +ve numbers are added(MSBs are 1), result is –ve (MSB is 1)
• Underflow: When two -ve numbers are added(MSBs are 1), result is +ve (MSB is 0)

Bit 31 Bit 0
MSB=0 , the number is +ve.
MSB=1 , the number is –ve.
32-bit data
Overflow Value1 + value2 > +2,147,483,647
Range of If the result is above the line, it is overflowed.
valid value
7FFF FFFF Hex=
-Value2
+2,147,483,647
-Value1
0
-Value3
-Value4
8000 0000 Hex=
-2,147,483,648 Underflow
-Value3 - value4 < -2,147,483,648
Ceg2400 Ch3 assembly V.6b 20
 The general format of an assembly
instruction
• All instructions have this form:
• op{cond}{S} Rd, Rn, Operand2

• Op=“ mnemonic” representing the operation , e.g. mov, add , xor.

– The assembler convert this into a number called op-code
• Cond(optional) : e.g. "EQ"=Equal to zero (Z=1), "HI" Unsigned higher. The
instruction is executed only when the condition is satisfied.
– http://www.cse.cuhk.edu.hk/
%7Ekhwong/www2/ceng2400/ARM_Instruction_quick_reference.doc
• {S} (optional) : suffix: if specified, the result of the instruction will affect the
status flags N,Z,C,V in CPSR, e.g.
– ADD r0, r1, r2 ; r0 := r1 + r2, ;CPSR (N,Z,C,V flags will not be affected)
– ADDS r0, r1, r2 ; r0 := r1 + r2, ;CPSR (N,Z,C,V flags will be affected)
• Rd, Rn (optional ) are register numbers
• Operand2 (optional) : additional operands

Ceg2400 Ch3 assembly V.6b 22

 3) Data processing operations
• Arithmetic operations
• Logical operations (AND OR NOT etc.)
• Register MOVes (MOV MVN)
• Comparison Operations

Ceg2400 Ch3 assembly V.6b 23

 Arithmetic operations
• Here are ARM's arithmetic (add and subtract with carry) operations:

ADDS
ADDS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1++r2r2
ADCS
ADCS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1++r2r2++CC
SUBS
SUBS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1--r2
r2
SBCS
SBCS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1--r2
r2++CC--11
If you add the ‘s’ suffix to an op-code, the instruction will affect the CPSR
(N,Z,C,V flags)
e.g.
• ADD r0, r1, r2 ; r0 := r1 + r2, CPSR (NZCV flags will not be affected)
• ADDS r0, r1, r2 ; r0 := r1 + r2, CPSR (NZCV flags will be affected)

• Operands may be unsigned or 2's complement signed integers

• 'C' is the carry (C) bit in the CPSR - Current Program Status Reg

Ceg2400 Ch3 assembly V.6b 24

 Current Program Status Register (CPSR)
Exercise 3.2
Fill in the shaded areas.
Program counter PC =R15, #value = intermediate constant value
Address (H) Comments After instruction is run

•
PC PC (Hex) C R0(Hex) R1(Hex) R2 (Hex)
All registers R0-R2 are rest to 0 here 0 0 0 0

0000 1000 MOV r1,#15 ;r1=15 0000 1004 0 0000 0000 0000 000f 0

MOV r2,#0xffffffff ;r2=#0xffffffff

;i.e. r2= -1

ADDS r0,r1,r2 ;r0=r1+r2

ADCS r0,r1,r2 ;r0=r1+r2+C

SUBS r0,r1,r2 ;r0=r1-r2

SBCS r0,r1,r2 ;r0=r1-r2+C-1

Ceg2400 Ch3 assembly V.6b 25

 64 bits addition
• If 32 bits are not enough, extend the numbers to 64 bits, you need to use two
registers to hold one number, i.e. [r0,r1] and [r3,r2]. But
• Remember to convert the input into sign extended numbers before use.
• Positive num. – add 0’s to LHS e.g. 0000 0007h -> 0000 0000 0000 0007h
• Negative num. – add 1’s to LHS e.g. 8000 0010h ->FFFF FFFF 8000 0010h
– E.g. 64-bit addition in [r1,r0] to [r3 r2], save result in [r3,r2]
– Sign extend the numbers from 32-bit to 64-bit, see above
– ADDS r2,r2,r0; add low, save carry: (Reference, P156, [1])
;this is the addition of lower part of the 64-bit 2’s comp. num., we treat the
addition as binary addition it is not a 2’comp. addition, the carry is useful
– ADC r3,r3,r1 ; add high with carry:
;this the high part of the 64-bit addition, we treat it as a 2’comp. addition, so
the carry generated is ignored
– ;Range of a 64-bit number is from -2^(64-1) to +2^(64-1) - 1 , or
from −9,223,372,036,854,775,808 to 9,223,372,036,854,775,807
• [1] ARM system-on-chip architecture by Steve Furber Addison Wesley
• [2] http://pages.cs.wisc.edu/~smoler/x86text/lect.notes/arith.int.html
26
Ceg2400 Ch3 assembly V.6b
Use of Carry C bit in the status flag
– ADDS r2,r2,r0; add low, save carry: (Reference, P156, [1])
;this is the addition of lower part of the 64-bit 2’s comp. num., we treat the
addition as binary addition it is not a 2’comp. addition, the carry is useful
Add data in r2 and data in r0, and save result in r2
– ADC r3,r3,r1 ; add high with carry:
;this the high part of the 64-bit addition, we treat it as a 2’comp. addition, so
the carry generated is ignored
Add data in r3 and data in r1, and save result in r3
– For binary addition: C is used.
– For 2’s complement, C is ignored. Since the Most
Significant bit is the sign bit so the C bit is
irrelevant, ,but you need to use the V bit to check
if the arithmetic calculation (e.g. add, sub) is
correct or not. Ceg2400 Ch3 assembly V.6b 27
 Logical operations (and, or,
exclusive or bit clear)
ANDS
ANDS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1and
andr2r2(bit-by-bit
(bit-by-bitfor
for32
32bits)
bits)
ORRS
ORRS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1or
orr2
r2
EORS
EORS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1xor
xorr2
r2
BICS
BICS r0,
r0,r1,
r1,r2
r2 ;;r0
r0:=
:=r1
r1and
andnot
notr2
r2
• N is set when the result is negative -- most significant bit is 1 when viewed as a
two’s-compliment number (appendix 1).
• CPSR
Z flag is set if the result is 0.
• The C and V flags are not affected.
• BIC stands for 'bit clear', where every '1' in the second operand clears the
corresponding bit in the first, (BICs r0, r1, r2) generates the following result:
r1: 0101 0011 1010 1111 1101 1010 0110 1011
r2: 1111 1111 1111 1111 0000 0000 0000 0000
r0: 0000 0000 0000 0000 1101 1010 0110 1011

Ceg2400 Ch3 assembly V.6b 28

 Current Program Status Register (CPSR)
Exercise 3.3
Fill in the shaded areas.
Program counter PC =R15, #value = intermediate constant value
Address (H) Comments After instruction is run
PC • R0(Hex) R1(Hex) R2(Hex) NZ
At the beginning 0000 0000H 0000 0055H 0000 0061H 00

0000 7000 ANDS r0,r1,r2 ;r0=r1 and r2 (bit

by bit )
ORRS r0,r1,r2 ;r0=r1 or r2

EORS r0,r1,r2 ;r0=r1 xor r2

BICS r0,r1,r2 ;r0=r1 and (not r2)

R1=55H=0101 0101 B
R2=61H=0110 0001 B
9EH=1001 1110 B

Ceg2400 Ch3 assembly V.6b 29

 Register MOVes
• Here are ARM's register move operations:

MOV
MOV r0,
r0,r2
r2 ;;r0
r0:=
:=r2
r2
MVN
MVN r0,
r0,r2
r2 ;;r0
r0:=
:=not
notr2
r2

• MVN stands for 'move negated‘, MVN r0, r2

if r2: 0101 0011 1010 1111 1101 1010 0110 1011

then r0:1010 1100 0101 0000 0010 0101 1001 0100

Ceg2400 Ch3 assembly V.6b 30

 Current Program Status Register (CPSR)
Exercise 3.4
Fill in the shaded areas.
Program counter PC =R15, #value = intermediate constant value
Address (H) Comments After instruction is run
PC • R0(Hex) R1(Hex) R2(Hex)
At the beginning 0 0000 0003H 0000 0007H

0000 8000 MOV r2,#12 ;r2=#12

MOV r0,r2 ;r0=r2

MVN r1,r2 ;r1= not r2

Hint : decimal 12=1100(Binary)=C (HEX)

Ceg2400 Ch3 assembly V.6b 31

 Comparison Operation1: CMP
• Here are ARM's register comparison operations:

CMP
CMP r1,
r1,r2
r2 ;;set
setcondition
conditioncode
codeon
onr1
r1--r2
r2(compare)
(compare)

• Same as SUB (subtract) except result of subtraction is not stored.

• Only the condition code bits (cc) {N,Z,C,V} in CPSR are changed

• N = 1 if MSB of (r1 - r2) is '1‘ (MSB of result is sign bit, 1 = negative)

• Z=1 when the result is zero
• C=1 when a binary addition generates a carry out; (for 32-bit integer 2’s
complement addition, C is ignored, see appendix.)
• V=1 (when result of add, subtract, or compare is >= 231, or < –231.). I.e.
• if two -ve numbers are added, the result is +ve (underflow), then V=1.
• if two +ve numbers are added, the result is -ve (overflow), then V=1
• If the two numbers are of different signs, no over/underflow, then V=0.
Ceg2400 Ch3 assembly V.6b 32
read (page 129, ARM Assembly Language Programming. Peter Knaggs)
 Exercise 3.5 , Fill in the shaded areas.
Address (H) Comments After instruction is run
PC NZCV (binary) R1 (Hex) R2 (Hex)
All registers R0-R2=0 and NZCV=0000 (binary), here

•
0000 1000 MOV r1,#0x11 ;r1=0000 0011

MOV r2,#0x23 ;r2=0000 0023

CMP r1, r2 ; set cc on r1 - r2

(compare)

MOV r1,r2 ; r1<=r2

CMP r1, r2 ; set cc on r1 - r2

(compare)

• N = 1 if MSB of (r1 - r2) is '1‘ (MSB of result is sign bit, 1 = negative)

• Z=1 when the result is zero
• C=1 when a binary addition generates a carry out; (for 32-bit integer 2’s
comp. addition, C is ignored, see appendix.)
• V=1 (when result of add, subtract, or compare is >= 231, or < –231.). I.e.
• if two -ve numbers are added, the result is +ve (underflow).
• if two +ve numbers are added, the result is -ve (overflow).
• If the two numbers are of different signs, no overflow/underflow.
Ceg2400 Ch3 assembly V.6b 33
 Comparison Operation 2: TST
• Here are ARM's register test operations:
TST
TSTr1,
r1,r2
r2 ;;set
setcc
ccon
onr1
r1and
andr2
r2(test
(testbits)
bits)

• Same as AND (logical AND) except result of operation is

not stored.
• Only the condition code bits (cc) {N,Z,C,V} in CPSR are
changed.
– updates the N and Z flags according to the result
– Does not affect the C or V flags.

Ceg2400 Ch3 assembly V.6b 34

 Other comparison Operations
• Here are ARM's register comparison operations:
CMP
CMP r1,
r1,r2
r2 ;;set
setcc
ccon
onr1
r1--r2
r2(compare)
(compare)
CMN
CMN r1,
r1,r2
r2 ;;set
setcc
ccon
onr1
r1++r2r2(compare
(comparenegative)
negative)
TST
TST r1,
r1,r2
r2 ;;set
setcc
ccon
onr1
r1and
andr2 r2(test
(testbits)
bits)
TEQ
TEQ r1,
r1,r2
r2 ;;set
setcc
ccon
onr1
r1xor
xorr2r2 (test
(testequivalent)
equivalent)

• Results of CMP (subtract), TST(AND) are NOT stored in

any registers
• Only the condition code bits (cc) {N,Z,C,V} in the CPSR
are set or cleared by these instructions:

Ceg2400 Ch3 assembly V.6b 35

 TST updates the N and Z flags
Exercise 3.6 according to the result, It
does not affect the C or V flags.
Fill in the shaded areas.

Address (H) Comments After instruction is run

PC NZCV (binary) R1 (Hex) R2 (Hex)
• All registers R0-R2=0 and NZCV=0000, here

0000 1000 MOV r1,#15 ;r1=15 decimal

MOV ;r2=0xF0 (0xf is

r2,#0240 240 in decimal)
TST r1,r2 ; set cc on r1
AND r2 (logical
AND operation
test bits)

TEQ r1,r2 ; set cc on r1 xor

r2 (test
equivalent)
Convert hex to decimal :http://easycalculation.com/hex-converter.php
E.g. 0000 1111 E.g. 0000 1111
And 0001 1000 Xor 0001 1000
--------------------------------- ---------------------------------
Result 0000 1000 Result 0001 0111 36
Ceg2400 Ch3 assembly V.6b
 Exercise 3.7:Self revision exercises
• Explain the purposes of having
– R14 (Link register) and R15 (PC program counter) in procedure
calls
• Explain how the N (negative) flag is affected by the ADDs
operation.
• Explain how the Z (zero) flag is affected by the ANDs
operation.
• Explain how the V (overflow) flag is affected by the CMP
operation.
• Assume there are some values in registers r0,r1,r2. Write
a program to find the result of r0+r1-r2 and save the
result in r3.

Ceg2400 Ch3 assembly V.6b 37

Self study programming exercise:;ex3_2400 ch3 of • ex3_2b ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
CENG2400. It is for your own revision purpose, no • movs r0,#1 ; this clears N,Z
need to submit answers to tutors. • adds r0,#1 ; this clears C,V
• ;http://www.cse.cuhk.edu.hk/ • mov r1,#0x7ffffffF ;=the biggest 32-bit 2's
%7Ekhwong/www2/ceng2400/ex3_2400_qst.txt complement num. +2,147,483,647
; ;declare variables • mov r2,#0x1
• ;Important: AREA starts from 2 or higher • ADDS r0,r1,r2;r0=0x80000000.
• AREA |.data|, DATA, READWRITE;s • ;Question2: explain the result in cpsr.
• Data1p DCD 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 • ex3_2c ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• align;----- • movs r0,#1 ; this clears N,Z
• ; User Initial Stack & Heap • adds r0,#1 ; this clears C,V
• AREA |.text|, CODE, READONLY • ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• EXPORT __main • mov r1,#0x7ffffffE ;=the 2nd biggest 32-bit
• __main LDR R0, =Data1p 2's complement num. +2,147,483,647-1
• ;;;;;;;;;;;; CEG2400 ex3_2 • mov r2,#0x1
• loop_top • ADDS r0,r1,r2; ;
• ;clear flags • ;Question3: explain the result in cpsr.
• ex3_2a ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; • ex3_2D ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• movs r0,#1 ; this clears N,Z • movs r0,#1 ; this clears N,Z
• adds r0,#1 ; this clears C,V ;;;;;;;;;;;;;;;;;; • adds r0,#1 ; this clears C,V
• mov r1,#15 ;r1=15 • ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• mov r2,#0xffffffff ; in 2' complement it is -1. • mov r1,#0xFffffffF ; THE VALUE IS -1 IN 2'S
• ADD r0,r1,r2 COMPLEMENT
• ADC r0,r1,r2 ;r0=r1+r2+C • mov r2,#0x1 ; IS 1
• SUB r0,r1,r2 ;r0=r1-r2 • ADDS r0,r1,r2; ;
• SBC r0,r1,r2 ;r0=r1-r2+C-1 • ;Question4: explain the result in r0 and cpsr.
38
• ;Question1: explain the result in r0 and cpsr of Ceg2400 Ch3 assembly V.6b
• ex3_3;;;;;;;;;;;; continue CEG2400 ex3_3 • ;Question12: explain result in r0->r12 and cpsr.
• movs r0,#1 ; this clears N,Z • ex3_6a ; place ex6
• adds r0,#1 ; this clears C,V • movs r0,#1 ; this clears N,Z
• ;;;;;;;;;;;;;;;;;;;
• mov r1,#0x55
• adds r0,#1 ; this clears C,V
• mov r2,#0x61 • ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• and r0,r1,r2 ; • mov r1,#15 ;r1=15 decimal=0xf=0000 1111 (lsb 8 bits)
• ;Question5: explain the result in r0 and cpsr. • mov r2,#24 ;r2=24 =0x18 =0001 1000 (lsb 8 bits)
• orr r0,r1,r2 ;r0=r1 or r2 • TST r1,r2 ;
• EOR r0,r1,r2 ; • ;Question13: explain the result in r0->r12 and cpsr.
• ;Question6: explain the result in r0 and cpsr.
• BIC r0,r1,r2;Question:
• ;not saved to any registers) is neither nagative nor zero
• ;Question7: explain the result in r0 and cpsr. • ; (bits c,v are not affected by tsts)
• ex3_4 ;;;;;;;;;;;;;;;;;;;;;;;;; • movs r0,#1 ; this clears N,Z
• movs r0,#1 ; this clears N,Z • adds r0,#1 ; this clears C,V
• adds r0,#1 ; this clears C,V;;;;;;;;;;;;;;;;;;;;;;;;;;;; • TEQ r1,r2 ;
• MOV r1,#0x3 • ;Question14: explain the result in r0->r12 and cpsr.
• MOV r2,#0x7
• MOV r2,#12 ;r2=#12
• ex3_6b ; place ex6
• MOV r0,r2 ; • movs r0,#1 ; this clears N,Z
• ;Question8: explain the result in r0 and cpsr. • adds r0,#1 ; this clears C,V
• MVN r1,r2 ;Quest: explain the result in cpsr. • ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
• ;Question9: explain result in r0 and cpsr. • mov r1,#0x0f ;15=0x0f= 0000 1111 (the least
• ex3_5 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; significant 8 bits)
• movs r0,#1 ; this clears N,Z • mov r2,#0xf0 ;r2=0x18= 1111 0000 (the least
• adds r0,#1 ; this clears C,V ;;;;;;;;;;;;;;;;; significant 8 bits)
• mov r1,#0x11 ;r1=0000 0011 (the LSB 8 bits)
•
• TST r1,r2 ;
mov r2,#0x23; r2=0000 0023
• subs r3, r1, r2 • ;Question15: explain the result in r0->r12 and cpsr.
• ;Question10: explain the result in r3 and cpsr. • movs r0,#1 ; this clears N,Z
• movs r0,#1 ; this clears N,Z • adds r0,#1 ; this clears C,V
• adds r0,#1 ; this clears C,V • TEQ r1,r2 ;
• cmp r1,r2; ; • ;Question16: explain the result in r0->r12 and cpsr.
• ;Question11: explain the result in r0->r12 and cpsr.
• mov r1,r2; ; r1<=r2
• END
• CMP r1, r2;
Ceg2400 Ch3 assembly V.6b 39
 End

Ceg2400 Ch3 assembly V.6b 40

 Appendix 1
Numbers and Arithmetic Operations

Ceg2400 Ch3 assembly V.6b 41

 Binary numbers
• Binary numbers (0, 1) are used in computers as they
are easily represented as off/on electrical signals
• Different number systems are used in computers
• Numbers represented as binary vectors
• B=bn-1…b1b0
• Unsigned numbers are in range 0 to 2n-1 and are
represented by V(B)=bn-12n-1 +…+b1 21 +b0 20
• MSB=Most significant bit (leftmost digit in a binary
vector)
– E.g. 0010 0101 binary =
25H=2^5+2^2+2^0=32+4+1(decimal)=37(decimal), because b5=1,
b2=1, b0=1 (bit5 ,bit2 and bit 0 are 1).
• LSB=Least significant bit (rightmost digit in a binary
Ceg2400 Ch3 assembly V.6b 42
vector)
 Negative Numbers
• Sign-and-magnitude
– The most significant bit (the left most bit) determines the sign,
remaining unsigned bits represent magnitude
• 1’s complement
– The most significant bit determines the sign. To change sign
from unsigned to negative, invert all the bits
• 2’s complement
– The most significant bit determines the sign. To change sign
from unsigned to negative, invert all the bits and add 1
– This is equivalent to subtracting the positive number from 2n
– See the following slide for examples.

Ceg2400 Ch3 assembly V.6b 43

 Binary Decim Hex

Number Systems 0000

al
0 0
Convert hex to decimal : http://easycalculation.com/hex-converter.php
http://www.rapidtables.com/convert/number/hex-to-decimal.htm 0001 1 1

B V alue represented
0010 2 2
0011 3 3
Sign and
b3 b2b1b0 magnitude 1' s complement 2' s complement 0100 4 4
0101 5 5
0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6 0110 6 6
0 1 0 1 +5 +5 + 5
+4 +4 + 4
0111 7 7
0 1 0 0
0 0 1 1 +3 +3 + 3 1000 8 8
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1 1001 9 9
0 0 0 0 +0 +0 + 0 1010 10 A
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7 1011 11 B
1 0 1 0 - 2 -5 - 6
1100 12 C
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4 1101 13 D
1 1 0 1 - 5 -2 - 3
- 6 - 1 - 2
1110 14 E
1 1 1 0
1 1 1 1 - 7 -0 - 1 1111 15 F
Ceg2400 Ch3 assembly V.6b 44
 Addition (1-bit)

0 1 0 1
+ 0 + 0 + 1 + 1
0 1 1 10

Carry-out

Ceg2400 Ch3 assembly V.6b 45

 2’s Complement
• 2’s complement numbers actually make sense since they follow normal
modulo arithmetic except when they overflow
• Range is -2n-1 to 2n-1-1

0 0000
1111 0001
N- 1 1
N-2 1110 0010
2 -1 0 +1
- 2 +2
1101 0011
- 3 +3

1100 -4 +4 0100
-5 +5
1011 0101
- 6 +6
- 7 - 8 +7
1010 0110
1001 0111
1000
(a) Circle representation of integers mod N (b) Mod 16 system for 2's-complement numbers

Ceg2400 Ch3 assembly V.6b 46

 Convert decimal to 2’s complement

• Negative number to 2’s complement

– From the positive value to binary
– Reverse all bits and add 1
– E.g. convert -5
– Positive value of 5 is 0101
– Reverse all bits 1010 and add one becomes
– 1011, SO the 2’s complement of -5 of 1011

Ceg2400 Ch3 assembly V.6b 47

 Convert 2’s complement to decimal
• If the first MSB is 0, convert binary to decimal as usual
• If the first MSB is 1, it is negative, the value can be found by
– Subtract 1
– Reverse all bit and get the value
– Add –ve sign to the value, e.g.
• Convert 1011, it is negative because MSB is 1
• Subtract 1 from 1011 becomes 1010,
• Reverse all bits becomes 0101, so the value is 5
• Add –ve sign so the decimal value of the 2’s complement number
1011 is -5.
• Reference: Introduction to Computing Systems: From Bits and Gates
to C and Beyond, By Yale N. Patt

Ceg2400 Ch3 assembly V.6b 48

 Add/sub
• X+Y : use 1-bit addition propagating carry to
the next more significant bit
• X-Y : add X to the 2’s complement of Y

Ceg2400 Ch3 assembly V.6b 49

 Add/Sub (2’s comp)
(a) 0010 (+2) (b) 0100 (+4)
+ 0011 (+3) + 1010 (- 6)
0101 (+5) 1110 (- 2)
(c) 1011 (- 5) (d) 0111 (+7)
+ 1110 (- 2) + 1101 (- 3)
1001 (- 7) 0100 (+4)
(e) 1101 (- 3) 1101
- 1001 (- 7) + 0111
0100 (+4)
(f) 0010 (+2) 0010
- 0100 (+ 4) + 1100
1110 (- 2)
(g) 0110 (+6) 0110
- 0011 (+3) + 1101
0011 (+3)
(h) 1001 (- 7) 1001
- 1011 (- 5) + 0101
1110 (- 2)
(i) 1001 (- 7) 1001
- 0001 (+1) + 1111
1000 (- 8)
(j) 0010 (+2) 0010
- 1101 (- 3) + 0011
0101 (+ 5) 50
Ceg2400 Ch3 assembly V.6b
 Sign Extension
• Suppose I have a 4-bit 2’s complement number and I
want to make it into an 8-bit number
• The reason to extend the bits is to avoid overflow (see
following slides)
• Positive number – add 0’s to LHS
– e.g. 0111 -> 00000111
• Negative number – add 1’s to LHS
– e.g. 1010 ->11111010
– c.f. circle representation

Ceg2400 Ch3 assembly V.6b 51

 Overflow and Underflow
see http://www.khmerson.com/~eia213/binnum.ppt

• Overflow
– When two +ve numbers are added (MSB is 0) , the
result is –ve (MSB is 1)
• Underflow
– When two -ve numbers are added (MSB is 1) , the
result is +ve (MSB is 0)
• Note:
– MSB is the most significant bit
– In 2’s complement representation MSB is the sign
bit (see appendix)
Ceg2400 Ch3 assembly V.6b 52
 Overflow
The result is too big for the bits
• In 2’s complement arithmetic
– addition of opposite sign numbers never overflow
– If the numbers are the same sign and the result is the opposite
sign, overflow has occurred (Range is -2n-1 to 2n-1-1). Usually CPU
overflow status bit will be setup and use software to deal with
it.
– E.g. 0111+0100=1011 (but 1011 is -5)
– 7 + 4= 12 (too large to be inside the 4-bit 2’s)
– Because 4-BIT 2’S complement range is only -23 to 23-1
– Or -8 to 7

Ceg2400 Ch3 assembly V.6b 53

 Range of 2’s complement numbers
See http://en.wikipedia.org/wiki/Integer_(computer_science)

• Previous examples are small numbers. In our usual programs they are
bigger.
• What is the range for a signed char type -- -- char (8-bit number)?
• What is the range for a signed integer type -- int32 (32-bit number)?
• What will you do if the result is overflowed?
• Answer: sign extension, see previous slides, e.g., turn a 4-bit number to 8-bit
etc.
• Positive number – add 0’s to LHS
– e.g. 0111 -> 00000111
• Negative number – add 1’s to LHS
– e.g. 1010 ->11111010

Ceg2400 Ch3 assembly V.6b 54

 Rules of using 2’s complement
• For a 32-bit machine, range of an integer is from
– -2^(32-1) to +2^(32-1) - 1 , or
– 8000 0000 H (-2,147,483,648 ) to 7FFF FFFF Hex
(+2,147,483,647)
– Addition of two 32-bit integers: if the result is outside this
range, the overflow bit in CPSR (V) will be set. E.g. adding
two large +ve numbers or adding two –ve numbers.
– Adding one +ve and one –ve number never generates
overflow.
– There is no need to look at the carry bit because it is not
relevant. The 2’s complement number uses the MSB as the
sign bit, the offset value encoded is only 31 bits long. Signs
of the results are handled automatically.
– See http://en.wikipedia.org/wiki/Two's_complement
Ceg2400 Ch3 assembly V.6b 55
 Characters
• Typically represented by 8-bit numbers

Ceg2400 Ch3 assembly V.6b 56

 Exercise
• Assuming 4-bit 2’s complement numbers
– What is the binary for -2?
– Calculate 2+3
– Calculate -2-3
– Calculate 5+5
• Assuming 5-bit numbers
– What is the largest 2’s complement number?
– What is the smallest 2’s complement number?
• Convert 56 to unsigned binary
• (http://www.wikihow.com/Convert-from-Decimal-to-Binary)
• What is the decimal value of 10110101 in 2’s complement? What is the
unsigned value of the same binary number?

Ceg2400 Ch3 assembly V.6b 57

 Appendix
from http://www.heyrick.co.uk/assembler/notation.html

• &
• The ampersand (&) is used to denote hexadecimal.
Thus,
• 0xF00D
• hF00D
• F00Dh
• $F00D (see later comment on the use of $) &F00D are all
identical, but using different ways to denote base 16. We
shall be using the &F00D notion.

Ceg2400 Ch3 assembly V.6b 58