AMERICAN INTERNATIONAL UNIVERSITY – BANGLADESH

(AIUB) Where leaders are created

Simple As Possible Computer

(SAP-1)
Lecture-3

Department of EEE
 SAP-1 Introduction
• SAP-1 is the first stage in the
evolution towards modern
computers.
• The main purpose of SAP is to
introduce all the crucial ideas
behind computer operations.
• Being a simple computer, SAP-1
also covers many advanced
concepts.
• SAP-1 is a bus organized
computer. All registers are
connected to the W bus
with the help of tri-state
buffers. SAP-1 Block Diagram
2 2
 Main Features of SAP-1
 Simple-As-Possible.  8-bit "W" bus.
 One output device with 8  4-bit program counter, only counts
up, it starts counting from 0 and
LEDs
counts up to 15.
 16 bytes of read only  4-bit Memory Address Register
memory. (MAR).
 5 instructions  16 Byte Memory.
o 3 with 1 operand,
 8-bit (1 Byte) Instruction Register
o 2 with implicit operands. (IR).
 Accumulator Architecture  6-cycle controller with 12-bit
• Accumulator, microinstruction word.
Output Register,  8-bit Accumulator.
• B Register,
Memory Address Register  8-bit B Register.
(MAR),  8-bit adder/subtractor.
• Instruction Register (IR).  8-bit Output Register.
3 3
 SAP-1 Architecture
Program Counter:
• Instructions (within a program) to be executed are placed at the starting
addresses of memory, e.g. the first instruction of a program will be placed at
binary address 0000. the second at address 0001. Now to execute one
instruction, first step is to generate the address at which this instruction is placed
in memory.
• Program counter keeps track of next instruction to be fetched and executed. So
this address is generated by (4-bit) Program Counter, that counts from 0000 to
1111 (for total of 16 memory locations).
• Program counter is like a pointer register; it points to the address in memory
where next instruction to be executed.
• If the value of program counter is 0100, then the instruction at address
location 4 will be executes next.
4 4
 SAP-1 Architecture (continued)

Input and Memory Address Register(MAR):

• These two switch registers allow to send 4 bits and 8 bits of data at a
time, during a computer run, addresses in Program counter is latched
into memory address register.
• The MAR stores the (4-bit) address of data and instruction which are
placed in memory.
• When SAP-1 is in Running Mode, the (4-bit) address is generated by the
Program Counter which is then stored into the MAR through W bus.
• A bit later, the MAR applies this 4-bit address to the RAM, where Data or
instruction is read from RAM.

5 5
 SAP-1 Architecture (continued)

RAM:
• In initial design, the RAM is a 16 x 8 static TTL RAM. It means there are
16 memory locations (from 0 to 15) and each location contains an 8-bit
of data/instruction.
• You can program the RAM by means of the switches to be used for
address and data. This allows you to store a program and data in the
memory before a computer run.
• During a computer run, the RAM receives 4-bit addresses from the
MAR and a read operation is performed,
• in this way, the instruction or data stored in the RAM is placed on the W
bus for use in some other part of the computer. 6 6
 SAP-1 Architecture (continued)

Instruction Register:
• When the instruction is placed at W-bus from memory, the Instruction
Register stores this instruction on the next positive clock edge and loads it.
• The contents of the instruction register are split into two nibbles.
The upper nibble is a two-state output that goes directly to the block
labeled "Controller-sequencer“
The lower nibble is a three-state output that is read onto the W bus
when needed.

7 7
 SAP-1 Architecture(continued)
Accumulator:
• It is a buffer register to immediately
store data through each instruction.
• The Accumulator has two outputs.
o One output goes to the
adder/subtractor
o The other goes to the W through
tri-state buffers.
• It also stores the (answer of two
values) output of adder/subtractor
through w-bus, when LA is low.
• It’s value is appeared on w-bus when
EA is high, which can then be read by
output register.
8 8
 SAP-1 Architecture (continued)
Adder/Subtractor:
• SAP-1 uses a 2's complement
adder-subtractor. When input Su is
low (logic 0), the sum is:
S=A+B
• When Su is high (logic 1), the sum
is:
S = A + B’ + 1
• The Adder-subtractor is
asynchronous (unclocked
operation) and its contents change
as soon as the input changes.
• When EU is high, these contents
appear on the W bus.
9 9
 SAP-1 Architecture (continued)

Register B:
• To add/sub two 8-bit numbers A
and B, the B register stored the
number B.
• When data is available at W-bus
and LB goes low, at the positive
clock edge, W-bus loads that data
into B register .

• It supplies the number to be added

or subtracted from the contents of
accumulator to the
adder/subtractor.

10 10
 SAP-1 Architecture (continued)

Output Register:
• At the end of an arithmetic operation the accumulator contains the
word representing the answer,
• In the next positive clock edge when EA is high and LO is low, the
accumulator word gets loaded from W-bus into output register,
this can be called o/p port and connected to printer or drive
peripheral devices too.
• Now this value can be displayed to the outside world with the help
of LEDs or 7 Segments.
Binary Display:
• The binary display is a row of eight light-emitting diodes (LEDs).
• Because each LED connects to one flip-flop of the output port,
the binary display shows us the contents of the output port.
• But we are using 7-segments in simulation.
11 11
 SAP-1 Architecture (continued)
• 
Controller Sequencer:
• The 12 bits coming out of the Controller Sequencer form a word that controls
the rest of the computer. Before each operation a Clear (CLR) signal resets the
program counter to 0000 and wipes out the latest instruction in IR.

• The 12 wires carrying the control word are called the Control Bus. The control
word has the format:

• This word determines how the Program counter and IR registers will react to
the next positive clock (CLK) edge. For instance a high EP and a low LM means
that the contents of Program Counter are latched into MAR on the next
positive clock edge. As another example, a low CE and a low mean that the
addressed RAM word will be transferred to the accumulator on the next
positive clock edge.
12 12
 SAP-1 Instruction Set
• Computer is a useless hardware until it is programmed

• This means loading step-by-step instructions into the memory before the
start of a computer run.

• Before you can program a computer, however, you must learn its instruction
set, the basic operations it can perform. The SAP-1 instruction set follows.

13 13
 Memory-Reference Instructions
• LDA, ADD, and SUB are called memory-reference instructions
because they use data stored in the memory.
• OUT and HLT, on the other hand, are not memory reference
instructions because they do not involve the data stored in the
memory.
Mnemonics
• LDA, ADD, SUB, OUT, and HLT are the instruction set for SAP-1.
Abbreviated instructions like these are called mnemonics (memory
aids). Mnemonics are popular in computer work because they
remind you of the operation that will take place when the
instruction is executed.
14 14
 Op Codes of SAP-1
 To load instruction and data words into the SAP-1 memory , we
have to use some kind of code that the computer can interpret.
 The number 0000 stands for LDA, 0001 for ADD, 0010 for SUB,
1110 for OUT, and 1111 for HLT.
 Because this code tells the computer which operation to
perform, it is called an operation code (op code).
 Assembly language involves working
with mnemonics when writing a
program.
 Machine language involves
working with strings of 0s and 1s.
15 15
 Fetch Cycle
• The control unit is the key to a computer's automatic operation.
The control unit generates the control words that fetch and
execute each instruction.
• While each instruction is fetched and executed, the computer
passes through different timing states (T states), time intervals
during which register contents change.
• Ring Counter has an output of-
T = T6 T5 T4 T3 T2 T1
• At the beginning of a computer run, the ring word is-
T = 00 0001 = T1

16 16
 Ring Counter
• Successive clock pulses produce, ring words of
T = 000010 = T2
T = 000100 = T3
T = 001000 = T4
T = 010000 = T5
T = 100000 = T6
• Then, the ring counter resets to 00 00 01, and the cycle repeats.
• Each ring word represents one T state.
• The initial state T1 starts with a negative clock edge and ends with the
next negative clock edge.
• During this T state, the T1 bit out of the ring counter is high.
• During the next state, T2 is high; the following state has a high T3; then a
high T4; and so on.
• The ring counter produces six T states. Each instruction is fetched and
executed during these six T states.
• A positive CLK edge occurs midway through each T state.
17 17
Clock and Timing Diagram

18 18
 Address State
• The T1 state is called the address state because the address in the
program counter (PC) is transferred to the memory address register
(MAR) during this state.
• During the address state, EP and LM are active; all other control bits
are inactive. This means that the controller-sequencer is sending out
a control word of 5E3H during this state

19 19
 Increment State
• The T2 state is called the increment state because the program
counter is incremented.
• During the increment state, the controller-sequencer is producing
a control word of BE3H
• Only the CP bit is active in this state.

20 20
 Memory State
• The T3 state is called the memory state because the addressed
RAM instruction is transferred from the memory to the
instruction register.
• The only active control bits during this state are CE and LI , and the
word out of the controller-sequencer is 263H

21 21
 Fetch Cycle
• The address, increment, and memory states are called the fetch cycle of
SAP-l.
• During the address state, EP and LM arc active; this means that the program
counter sets up the MAR via the W bus.
• A positive clock edge occurs midway through the address state; this loads
the MAR with the contents of the PC.
• During the increment state, CP is the only active control bit.
• This sets up the program counter to count positive clock edges. Halfway
through the increment state, a positive clock edge hits the program counter
and advances the count by 1.
• During the memory state, CE and LI are active. The addressed RAM word
sets up the instruction register via the W bus. Midway through the memory
state, a positive clock edge loads the instruction register with the
addressed RAM word.
22 22
 Execution Cycle

• The next three states (T4, T5, and T6) are the execution cycle of SAP-
1.
• The register transfers during the execution cycle depend on the
particular instruction being executed.
• For instance. LDA 9H requires different register transfers than ADD
BH.
• What follows are the control routines for different SAP-1 instructions.

23 23
 LDA Routine
•• Assume
  instruction register loaded with LDA 9H, So IR =0000 1001
• During T4 state, the instruction field 0000 goes to the controller-sequencer,
where it is decoded; the address field 1001 is loaded into MAR. and are
active.
• During T5 State, and goes low. This means that the addressed data word in
the RAM will be loaded into the accumulator on the next positive clock
edge.
• T6 is no operation(NOP) state. All registers are inactive.

24 24
 Fetch and LDA timing Diagram
 • During T1 state, and are active. The +ve clock
edge midway through the state transfer the
address in the program counter to the MAR.
• During T2 state, is active and the program counter
incremented in the +ve clock cycle.
• During T3 state, and are active; when the +ve
clock edge occurs, the addressed RAM word is
transferred to the instruction register.
• The LDA execution starts with T4 state, where
and are active; On the +ve edge of the clock the
address field in the instruction register is
transferred to the MAR.
• During the T5 state, and are active; the
addressed RAM data word is transferred to the
accumulator on the +ve clock edge.
• T6 is NOP 25 25
 ADD
Routine
• 
• Suppose at the end of the fetch cycle the instruction register contains ADD BH: IR=
0001 1011
• During the T4 state, the instruction field goes to the controller sequencer and
address field to the MAR. and are active.
• During T5 state, and are active. This allows the addressed RAM word to set up B
register.
• During the T6 state, and are active. Therefore, the adder-subtractor sets up the
accumulator.

26 26
 Timing Diagram of fetch & ADD Routine

• During
  T4 state, and are active; on the
next positive clock edge, the address field
in the instruction register goes to MAR.
• During T5 state, and are active; therefore,
the addressed RAM word is loaded into the
B register at the +ve clock edge.
• During T6 state, and are active. When the
+ve clock edge hits, the sum out of adder-
subtractor is stored in the accumulator.

27 27
 SUB Routine

•  Similar to the ADD routine.

• Only differences is during T6 state, a high is sent to the adder-
subtractor.
• Timing diagram is almost identical except T6 state where is
active.

28 28
 OUT Routine

• Suppose
  the instruction register contains the
OUT instruction at the end of the fetch cycle.
Then, IR= 1110 XXXX.
• The instruction field goes to the controller
sequencer for decoding. Then the controller-
sequencer sends out the control word needed
to load the accumulator contents into the
output register.
• During T4 state, and are active. The next +ve
edge load the accumulator contents into the
output register during T4 state.
• T5 and T6 states are NOP.

29 29
 Fetch and Out Timing Diagram

•  Fetch cycle is same for all routine

(T1,T2 and T3)
• During T4 state, and are active; this
transfers the accumulator word to the
output register when the +ve clock
edge occurs.

30 30
 HLT Routine

• HLT does not require a control routine because no registers are

involved in the execution of an HLT instruction. When the IR
contains
IR= 1111 XXXX
• The instruction field 1111 signals the controller sequencer to
stop processing data.
• The controller sequencer stops the computer by turning off the
clock.

31 31
Micro Instructions
• The controller-sequencer sends out control words, on during each T state
or clock cycle.
• These words are like directions telling the rest of the computer what to
do.
• Because it produces a small step in the data processing, each control
word is called a micro-instruction.

Macro Instructions
• The instructions we have been programming with (LDA, ADD, SUB, . . .)
are sometimes called macro-instructions to distinguish them from micro-
instructions.
• Each SAP-1 macroinstruction is made up of three microinstructions. For
example, the LDA macroinstruction consists of the three
microinstructions shown in the next Table.
• This table shows the SAP-1 macro-instruction and the micro-instructions
needed to carry it out. 32 32
 Fetch and Execute Cycle of SAP-1
Macro Inst. T State Micro Operation Active CON
All Instructions T1 MAR ← PC L'M, EP 5E3H
33
T2 PC← PC+1 CP BE3H
T3 IR ← RAM[MAR] CE', L‘I 263H
LDA T4 MAR ← IR(3…0) L'M, E‘I 1A3H
T5 ACC ← RAM[MAR] CE', L'A 2C3H
T6 None None 3E3H
ADD T4 MAR ← IR(3…0) L'M, E‘I 1A3H
T5 B ← RAM[MAR] CE', L'B 2E1H
T6 ACC ← ACC+B L'A, EU 3C7H
SUB T4 MAR ← IR(3…0) L'M, E‘I 1A3H
T5 B ← RAM[MAR] CE', L'B 2E1H
T6 ACC ← ACC – B L'A, SU, EU 3CFH
OUT T4 OUT ← ACC EA, L'O 3F2H
T5 None None 3E3H
T6 None None 3E3H
HLT T3 None HLT ' 33 263H
 Machine Cycle & Instruction
Cycle

6 T states are called machine cycle

The Number of T states needed to fetch and execute an
instruction is called instruction cycle.
34
 SAP-1 Control Signals

Instru T1 T2 T3 T4 T5 T6
ction
LDA Ep Cp Ce’ Ei’ Ce’ X
Lm’ Li’ Lm’ La’
Fetch Cycle-
ADD Ep Cp Ce’ Ei’ Ce’ Eu
T1,T2,T3 Lm’ Li’ Lm’ Lb’ La’

Execution Cycle- SUB Ep Cp Ce’ Ei’ Ce’ Eu

Lm’ Li’ Lm’ Lb’ Su
T4,T5,T6 La’
OUT Ep Cp Ce’ Ea X X
Lm’ Li’ Lo’

HLT Ep Cp Ce’ X X X
Lm’ Li’

35 35
 State Equations
• Ep= T1
• Cp= T2
• Lm’= T1+ T4.LDA+T4.ADD+T4.SUB
• Ce’= T3+ T5.LDA+T5.ADD+T5.SUB
• Li’= T3
• Ei’= T4.LDA+T4.ADD+T4.SUB
• La’= T5.LDA+T6.ADD+T6.SUB
• Ea= T4.OUT
• Su= T6.SUB
• Eu= T6.ADD+T6.SUB
• Lb’= T5.ADD+T5.SUB
• Lo’= T4.OUT 36 36
 Microprogramming

• Reduces the complexity of control circuit.

• With large instructions control matrix become very complicated
and requires hundreds even thousands of gates.
• In Microprogramming, microinstructions are stored in a ROM
instead of producing them with hardwired control matrix.

37 37
 Storing the microprogram
Table: SAP-1 Control ROM
• By assigning addresses and including the Address CON Routine Active
fetch routine, come up with SAP-1 0H 5E3H Ep,Lm'
Fetch
microinstructions. 1H BE3H
 
Cp
2H 263H   CE',Li'
• These microinstructions can be stored in
3H 1A3H Lm',EI'
Control ROM with the fetch routine at 4H 2C3H LDA CE',La'
 
addresses shown in Table. 5H 3E3H   None
• To access any routine, we need to apply 6H 1A3H
ADD
Lm',EI'
7H 2E1H CE',Lb'
correct addresses. For instance to get 8H 3C7H
 
  La',Eu
ADD, apply 6H,7H and 8H. 9H 1A3H Lm',EI'
SUB
• Three steps of accessing routine AH 2E1H
 
CE',Lb'
BH 3CFH   La',Su,Eu
• Knowing the starting address CH 3F2H Ea,Lo'
• Stepping through the routine address DH 3E3H OUT
 
None
EH 3E3H   None
• Apply the address to the Control ROM FH X X NOT USED
38 38
Microprogrammed Controller circuit

39 39
 SAP-1 Address
ROM Table: Address ROM
Address Contents Routine
0000 0011 LDA
 • Microprogrammed Control Circuit of 0001 0110 ADD
SAP-1 has an address ROM, a pre- 0010 1001 SUB
settable counter and a control ROM. 0011 XXXX NONE

• The Address ROM contains the staring 0100 XXXX NONE

addresses of each routine. For instance 0101 XXXX NONE

0110 XXXX NONE
the starting address of LDA is 3H means
0111 XXXX NONE
0011.
1000 XXXX NONE
• When the opcode bits drive the 1001 XXXX NONE
address ROM, the staring address is 1010 XXXX NONE
generate. 1011 XXXX NONE
1100 XXXX NONE
1101 XXXX NONE
1110 1100 OUT
1111 40XXXX NONE40
 Microprogram SAP-1

• Pre-settable Counter
When T3 is high, the load input of the pre-settable counter is high and
the counter loads the starting address form the address ROM. During
the other T states the counter counts.

• Control ROM
The Control ROM store the SAP-1 microinstructions. During fetch
instructions it receives 0000, 0001 and 0010 therefore, the outputs are
5E3H,BE3H,263H

41 41
 Variable Machine Cycle

• There is A microinstruction called NOP. It occurs once in LDA and

twice in the OUT routine. These NOPs are used in SAP-1 to get a fixed
machine cycle for all instructions. In other words each machine cycle
takes exactly 6 T states. No matter what the instruction is.
• In some computers fixed machine cycle is advantage.
• But when speed is important, the NOPs are a waste of time and can
be eliminated.
• One way to speed up machine is to skip any T state with NOP. This
will shorten LDA instructions to 5 states and OUT instructions to 4
states. This is called variable machine cycle.

42 42
 Variable Machine Cycle
• Redesigned to speed up
machine cycle.
• With an LDA instruction, the
actions is same as before during
the T1 to T5 states.
• When T6 begins the control
ROM sends output 3E3H. The
NAND gates detect the NOP
instantly and produce a low
output signal, which is feedback
to a ring counter through an and
gate.
• This resets the ring counter to T1
states, and a new machine cycle
begins. 43 43
 Question

• What is the motivation behind Microprogramming? With

complete block diagram briefly explain the
controller/sequencer design using microprogramming
technique. Control word of the controller/sequencer is given.
• Specify SAP-1 Control ROM and Address ROM contents.

44 44