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Cmos Design: - MOS Transistors As A Switch - CMOS Inverter Characteristic - Basic Gates - Complex CMOS Design

Noise margin is a measure of noise immunity in digital circuits. It refers to the amount of noise that can be tolerated by a circuit before its output changes state. In CMOS circuits, there are two types of noise margins: 1. High noise margin (HNM): It is the minimum amount by which the input voltage must exceed the switching threshold of the input in order to ensure the output does not switch. 2. Low noise margin (LNM): It is the maximum amount by which the input voltage can fall below the switching threshold without causing the output to switch. Higher noise margins indicate greater noise immunity. During the design process, noise margins are maximized to ensure robust operation in the presence of noise

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108 views

Cmos Design: - MOS Transistors As A Switch - CMOS Inverter Characteristic - Basic Gates - Complex CMOS Design

Noise margin is a measure of noise immunity in digital circuits. It refers to the amount of noise that can be tolerated by a circuit before its output changes state. In CMOS circuits, there are two types of noise margins: 1. High noise margin (HNM): It is the minimum amount by which the input voltage must exceed the switching threshold of the input in order to ensure the output does not switch. 2. Low noise margin (LNM): It is the maximum amount by which the input voltage can fall below the switching threshold without causing the output to switch. Higher noise margins indicate greater noise immunity. During the design process, noise margins are maximized to ensure robust operation in the presence of noise

Uploaded by

Salim San
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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CMOS DESIGN

•MOS Transistors as a switch


•CMOS Inverter Characteristic
•Basic Gates
•Complex CMOS design
Strong 0

closes

closes
(N-Switch)
NMOS Pass Transistor

Drain and source terminals are


always interchangeable.
gate

Assume load capacitor is initially discharged (Vout=VSS).


With S=0 (VSS), the transistor is cutoff and irrespective of the
input VOUT =VSS.
To have conduction, either gate-source voltage or gate the drain
voltage have to be greater than threshold.
NMOS Pass Transistor
Drain and source
VDD VSS terminals are always
gate
interchangeable.
VDD

When S=1 (VDD), and Vin=1, the transistor is turned ON. Transistor
is ON because of the output is at VSS.
The pass transistor starts to conduct and charges the load
capacitor towards VDD. Current flows from left to right. As the
output voltage approaches VDD-VTN, n-type MOSFET begins to turn
off. The load capacitor will be charged at VDD-VTN when S is
changed back to 0 and remains there.
NMOS Pass Transistor
VDD
VSS

gate
VDD

With S=1, and Vin=1, the output voltage stays at VDD-VTN. This
implies that the transmission of logic one is degraded as it
passed through NMOS gate.
With S=1, and Vin=0, and assume Vout=VDD, the pass
transistor begins to conduct (since input is at VSS at all times,
transistor will stay ON forever) and discharge load capacitor
towards Vss. Current now flows from right to left.
Vout completely falls to Vss (0 V). The transmission of logic 0
in a NMOS is not degraded.
PMOS Pass Transistor (P-switch)
VSS

VDD For conduction, either source-gate or


drain-gate voltage has to be greater
gate than |Vtp|.
VSS

With -S=1, and Vin=1, assume load capacitor is initially


discharged (Vout=VSS). The transistor is cutoff and load
capacitor stays at Vout =VSS or at logic 0.
With (-S)=0, and Vin=1 (VDD), and Vout=VSS, the pass
transistor begins to conduct (since input is at VDD at all times,
transistor will stay ON forever) and charges load capacitor
towards VDD.
The transmission of logic one is not degraded as it passes
through PMOS gate.
PMOS Pass Transistor

VSS
VDD

gate
VSS

With (-S)=0, and Vin=0, and Vout=VDD, the transistor conducts


(because of VDD voltage currently at the capacitor) and the
load capacitor discharges through the p-device until Vout=|
Vtp|. Because at this point transistor stops conducting.
The transmission of logic 0 is degraded as it passes
through PMOS gate.
Transmission Gate Characteristics:
DEVICE Transmission of ‘1’ Transmission of ‘0’
n poor good
p good poor

By combining two gates together we obtain a perfect switch


FINAL RESULT

(When s=1 and –s=0 applied)


A transmission gate is a multiplexing element, based
on control input s, it passes data from a to b without
any attenuation.

If S=1 (-S=0), data is transmitted from a to b,


If S=0 (-S=1), data is not transmitted.
THE INVERTER
If we look at the CMOS inverter, we
observe that PMOS provides a path
to logic high ‘1’ when it is turned on.
PMOS is a good provider of logic 1
And it is turned on by logic 0.
NMOS provides a path to logic 0,
(NMOS is a good provider of logic 0)
Input Output when it is turned on. And it requires
0 1 a logic high ‘1’ at the input to turn on.
1 0
CMOS INVERTER

PMOS
PMOS
turns on
Cutoff

NMOS NMOS
turns on Cutoff

Switch Models of a CMOS inverter


#1

#2
#3

#4
AND FUNCTION

=NOR function with two series


AND function with inverted inputs.
PMOS.
OR FUNCTION

NAND function (OR function with inverted inputs)


To implement functions in CMOS, we will
implement f (logic 1) with PMOS and
f ’ with NMOS transistors.
F =( A.B )’ IMPLEMENT WITH PMOS
NAND FUNCTION ON PMOS SIDE

F ’ = A.B IMPLEMENT WITH NMOS


F =( A.B.C )’ IMPLEMENT WITH PMOS
F ’ = A.B.C IMPLEMENT WITH
NMOS
F=(A+B)’

F=(A+B)’ =A’.B’

F’=(A+B)

NOR fcn with PMOS

OR fcn with NMOS


Given a logic function to implement, it is easier to draw n-
side since p-side seems a little difficult.

From now on, we will first implement n side using F’ and


then for p-side we will take the DUAL of whatever we have
on the n-side.

i.e. if two NMOSs are parallel, we take the PMOS’s in


series and vice versa.
Example:

IMPLEMENT NMOS SIDE FIRST USING F


(VDD)

Vss

(VSS)
F
Example: F = a’(b+c)
b’
F’ = a +(b’c’) a

c’
Then the pulldown network:
Vss (0)
This is derived
taking the dual Vdd (1)
of above NMOS
The pull-up network is: block
b’ c’
NOTE:
Never use function F in drawing PMOS
block, derive PMOS block by taking the
dual of NMOS block.
block a
Remember to keep the variables same
in both blocks. F
VDD

Obtain PMOS block


b’ c’ after drawing NMOS
block and taking the
dual of it.

b’

a
F’ = a +(b’c’)
c’

GND
Another Example
=

NAND INVERTER
GATE
OR GATE

(I1.I2.I3.I4)'+(I5.I6.I7.I8)'= I1’+I2’+I3’+I4’+ I5’+I6’+I7’+I8’


= (I1.I2.I3.I4.I5.I6.I7.I8)’
Example :

Only the signals A,B,C,D and E are available.

If we had complement of signals available, First we would


take Y’
Y’=(A’+B’)(C’+D’E’) and implement with NMOS transistors
and take the dual for PMOS. But, here each complement
will cost us 2 transistors (total of 10 extra transistors).

But here since we do not have the complement of signals, the best
approach would be to implement Y’ (using Y for NMOS block and
taking the dual for PMOS). We could then put an INVERTER at the
end to obtain Y. We would use only 2 extra transistors instead of 10.
implement Y with NMOS

The whole gate will


implement Y’, therefore
we are implementing Y
with NMOS transistors
WHAT IS A NOISE MARGIN?

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