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1.8 Interrupts in 8051

The document discusses interrupts in microcontrollers. It describes what interrupts are, the difference between interrupts and polling, advantages of interrupts, the steps involved in processing an interrupt, interrupts in the 8051 microcontroller, the interrupt vector table, and the IP and IE registers used for enabling and disabling interrupts.

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Nithin Itteera
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49 views

1.8 Interrupts in 8051

The document discusses interrupts in microcontrollers. It describes what interrupts are, the difference between interrupts and polling, advantages of interrupts, the steps involved in processing an interrupt, interrupts in the 8051 microcontroller, the interrupt vector table, and the IP and IE registers used for enabling and disabling interrupts.

Uploaded by

Nithin Itteera
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Interrupts

• An interrupt is an external or internal event that interrupts the


microcontroller to inform it that a device needs its service
Interrupt versus polling
• A single microcontroller can serve several devices by two ways
1. Interrupt
• Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal
• Upon receiving an interrupt signal, the microcontroller interrupts whatever it
is doing and serves the device
• The program which is associated with the interrupt is called the interrupt
service routine (ISR) or interrupt handler
2. Polling
• The microcontroller continuously monitors the status of a given device
• When the conditions met, it performs the service
• After that, it moves on to monitor the next device until every one is serviced
Advantages of interrupts over polling
• The advantage of interrupts is that the microcontroller can serve
many devices
• Each devices can get the attention of the microcontroller based on
the assigned priority
• For the polling method, it is not possible to assign priority since it
checks all devices in a round-robin fashion
• The microcontroller can also ignore (mask) a device request for
service
• This is not possible for the polling method
Steps involved in processing an interrupt
• Upon activation of an interrupt, the microcontroller goes through the
following steps
• It finishes the instruction it is executing and saves the address of the next
instruction (PC) on the stack
• It also saves the current status of all the interrupts internally
• It jumps to a fixed location in memory, called the interrupt vector table, that
holds the address of the ISR
• The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it
• It starts to execute the interrupt service subroutine until it reaches the last
instruction of the subroutine which is RETI (return from interrupt)
• Upon executing the RETI instruction, the microcontroller returns to the place
where it was interrupted
Interrupts in 8051
• Reset – power-up reset
• Two interrupts are set aside for the timers: one for timer 0 and one
for timer 1
• Two interrupts are set aside for hardware external interrupts
• P3.2 and P3.3 are for the external hardware interrupts INT0 , and INT1
• Serial communication has a single interrupt
Interrupt vector table
• For every interrupt, there must be an interrupt service routine
• When an interrupt is invoked, the microcontroller runs the interrupt
service routine
• Address of ISR is sored in a fixed memory location
• The group of memory locations set aside to hold the addresses of ISRs
is called interrupt vector table
IP and IE registers
• Upon reset, all interrupts are disabled (masked), meaning that none
will be responded to by the microcontroller if they are activated
• The interrupts must be enabled by software in order for the
microcontroller to respond to them
• There is a register called IE (interrupt enable) that is responsible for
enabling (unmasking) and disabling (masking) the interrupts
• There is register called IP (Interrupt priority) for setting priorities of
interrupts

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