Fall 2020 ECE 445 - Computer Organization 1

PROCESSOR DESIGN, RTL,

AND THE MIPS
ECE 445 – Computer Organization
Dr. Craig Lorie
Electrical and Computer Engineering
Lecture #6
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Topics Covered
• Introduction to Processor Design
• Datapath and Control Unit
• Design requirements
• Using an internal CPU bus
• Introduction to Register Transfer Language (RTL)
• Describing CPU micro-operations using RTL
• Describing a processor using RTL
• Describing the MIPS using RTL
• Implementations of the MIPS Processor
• Single-cycle, Multi-cycle, Pipelined
• One-bus
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Reading Assignment
• Hennessey/Patterson: 4.1 – 4.4
• Hennessey/Patterson: 3rd Edition, 5.5 (on Blackboard)
• Additional reading posted on Blackboard.
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INTRODUCTION TO
PROCESSOR DESIGN
Architecture (ISA) and Organization (implementation)
Datapath and Control Unit
Design requirements
Using one or more buses
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Architecture and Organization

• Architecture (aka. Instruction Set Architecture)
• Describes what the processor can do.
• Specifies the instruction set, register set, addressing modes, etc.

• Organization (aka. Implementation or Microarchitecture)

• Describes how the processor implements the functionality described in
the architecture.
• Specifies the components, interconnections, control signals, etc.
• Can be multiple implementations of a single processor architecture.
• All implementations execute the same set of instructions.
• Different implementations may use different technologies.
• Different implementations have different cost/performance specs.
• Leads to a “family” of processors.
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Architecture and Organization

Architecture of a simple processor. Architecture of the Pentium processor.

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Computer Organization
• The processor can be partitioned into the:

1. Datapath
• Composed of functional blocks.
• Implements the actions necessary to fetch and execute all of the
instructions specified in the instruction set of the processor.

2. Control Unit
• Generates the control signals.
• Controls the components in the datapath.
• Value of each control signal determined during instruction decoding.
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Processor Design
• Design both the datapath and the control unit.
• Consider all instructions that are executed by the processor.
• Determines the components required in the datapath.
• Determines the required control signals.
• Consider cost, performance, and power consumption.
• Determines technology choice.
• Determines component selection.
• Design a family of processors.
• All processors adhere to the specified instruction set architecture (ISA).
• Each is designed to meet a different cost/performance/power
consumption specification.
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Internal CPU Bus

• In principle, we must make connections between datapath
components for every instruction.
• This, potentially, leads to all datapath components being connected to all
other datapath components.
• Numerous connections are expensive and take up valuable
space on the chip.
• Instead, use a set of wires that all components can connect to
and share in order to transfer information.
• Rather than using a dedicated set of wires between every pair of
datapath components.
• Results in a bus-based design for the datapath of the processor.
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CPU Bus(es) and Data Transfer

• The number of internal CPU buses used determines the number of data
words that can be transferred simultaneously (i.e. in the same clock cycle).
One-bus Organization Three-bus Organization

Only one data word can be Up to three data words can be

transferred each clock cycle. transferred each clock cycle.
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CPU Bus: Using Multiplexers

Bus3
4-line
Bus2
common
Bus1 Bus
Bus0

4x1 4x1 4x1 4x1

Mux3 Mux2 Mux1 Mux1
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
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CPU Bus: Using Tri-state Buffers

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Data Transfer between Registers

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Data Transfer between Registers

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INTRODUCTION TO RTL
Register Transfer Language (RTL)
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Register Transfer Language (RTL)

• Register transfer language
• A symbolic language
• A convenient tool for describing the internal organization of a computer.
• Can also be used to facilitate the design process of digital systems.
• RTL can be used to describe the sequence of micro-operations,
or actions, needed to implement any processor instruction.
• RTL is a concise and precise means of describing the
micro-operations that can be performed on the data stored in
the registers of a processor.
• RTL is a simple, human-oriented language to specify the
operations, register communication, and timing of the steps
implemented by the CPU for each user programmable instruction.
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Registers and RTL Expressions

• Registers are denoted by upper-case letters.
• Optionally followed by numbers or letters.

• RTL expressions
• Identify the registers to be manipulated
• Specify the micro-operations to be performed on the registers.
• Basic components of RTL expressions:
Symbol Description Example
Letters and Numbers Denotes a register R1, PC, MAR
Parentheses Denotes a part of a register R1(5 – 0), R2(17), MDR(31 – 16)
Left arrow Denotes transfer of information R1 <- R2
Comma Separates two micro-operations R1 <- R2, R3 <- R4
Colon Separates control from expression P: R1 <- R2
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RTL Micro-operations
• Each micro-operation, or action, is completed in one clock cycle.

• Concurrent (parallel) micro-operations

• Some micro-operations can be implemented at the same time.
• They are implemented in different parts of the processor.
• They are independent of one another.
• They are completed in the same clock cycle.
• Sequential micro-operations
• Other micro-operations must be implemented in sequence.
• They are dependent on one another.
• Each requires a clock cycle.
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Common RTL Micro-operations

• Data Transfer
RTL Description
R1 <- R2 Transfer (copy) contents of register R2 to register R1
(Requires one CPU bus)
R1 <- R2, R3 <- R4 Concurrent transfer
Transfer (copy) contents of R2 to R1 and contents of R4 to R3.
(Requires two CPU buses)
P: R1 <- R2 Conditional transfer
Transfer contents of R2 to R1, if (P = 1).
T: R1 <- R2, R3 <- R4 Conditional, concurrent transfer
Transfer contents of R2 to R1 and contents of R4 to R3, if (T = 1).

Data transfer micro-operations are implemented using the internal CPU bus(es).
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Common RTL Micro-operations

• Arithmetic
RTL Description
R3 <- R1 + R2 Contents of R1 plus contents of R2 transferred to R3
R3 <- R1 – R2 Contents of R1 minus contents of R2 transferred to R3
R2 <- R2’ 1’s Complement of R2
R2 <- R2’ + 1 2’s Complement of R2 (negate)
R3 <- R1 + R2’ + 1 R1 plus 2’s Complement of R2 (R1 – R2) transferred to R3
R1 <- R1 + 1 Increment contents of R1 by 1
R1 <- R1 – 1 Decrement contents of R1 by 1

Arithmetic micro-operations are implemented by the ALU.

Multiplication and division are not considered micro-operations.

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Common RTL Micro-operations

• Logic
RTL Description
R3 <- R1 and R2 Contents of R1 ANDed with contents of R2 transferred to R3
R3 <- R1 or R2 Contents of R1 ORed with contents of R2 transferred to R3
R1 <- R1’ Complement of R1 (NOT)
R3 <- R1 xor R2 Contents of R1 XORed with contents of R2 transferred to R3
R3 <- (R1 and R2)’ Contents of R1 NANDed with contents of R2 transferred to R3
R3 <- (R1 or R2)’ Contents of R1 NORed with contents of R2 transferred to R3
R3 <- (R1 xor R2)’ Contents of R1 XNORed with contents of R2 transferred to R3

Logic micro-operations are implemented by the ALU.

Most systems only implement AND, OR, NOT, and XOR.

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Memory Transfer
• Read A read operation transfers data from memory to a register.
RTL Description
MAR <- address Copy address into Memory Address Register (MAR)
MDR <- M[MAR] Transfer data from memory at address in MAR to
Memory Data Register (MDR)

• Write A write operation transfers data from a register to memory.

RTL Description
MAR <- address Copy address into Memory Address Register (MAR)
M[MAR] <- MDR Transfer data from Memory Data Register (MDR) to
memory at address in MAR.
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DESCRIBING THE MIPS

ARCHITECTURE USING RTL
Registers
Memory
Instruction Formats
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MIPS Instruction Set Architecture

• MIPS is a 32-bit processor
• ALU operands are 32 bits
• Registers are 32 bits
• Registers
• Thirty-two, 32-bit registers (general purpose, SP, FP, RA, etc.)
• Program Counter (PC), Instruction Register (IR)
• Memory Address Register (MAR), Memory Data Register (MDR)
• Instruction Formats: R-type, I-type, and J-type
• Memory system
• 32-bit address
• Byte-addressable memory
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Registers and Memory

Registers RTL Description
Thirty-two 32-bit registers R[0..31](31 – 0)
(Register File)
32 registers 32 bits (MSb = bit 31)
Program Counter (PC) PC(31 – 0)
Instruction Register (IR) IR(31 – 0)
Memory Address Register (MAR) MAR(31 – 0)
Memory Data Register (MDR) MDR(31 – 0)

Memory RTL Description

Address width = 32 bits M[0..232 – 1](7 – 0)
Byte-addressable
232 memory locations 1 byte (8 bits)
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Instruction Formats: R-type

31 26 25 21 20 16 15 11 10 6 5 0
opcode Rs Rt Rd shamt funct R-type

Field name Bits of Instruction Register (IR)

opcode(5 – 0) IR(31 – 26)
Rs(4 – 0) IR(25 – 21)
Rt(4 – 0) IR(20 – 16)
Rd(4 – 0) IR(15 – 11)
shamt(4 – 0) IR(10 – 6)
funct(5 – 0) IR(5 – 0)
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Instruction Formats: I-type

31 26 25 21 20 16 15 0
opcode Rs Rt immediate I-type

Field name Bits of Instruction Register (IR)

opcode(5 – 0) IR(31 – 26)
Rs(4 – 0) IR(25 – 21)
Rt(4 – 0) IR(20 – 16)
Immediate (15 – 0) IR(15 – 0)
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Instruction Formats: J-type

31 26 25 0
opcode address J-type

Field name Bits of Instruction Register (IR)

opcode(5 – 0) IR(31 – 26)
address(25 – 0) IR(25 – 0)
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THE MIPS PROCESSOR

Single-cycle, multi-cycle, and pipelined implementations
One-bus implementation
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MIPS
• Microprocessor without Interlocked Pipeline Stages.
• Reduced Instruction Set Computer (RISC)
• Additional information can be found at the following website:
http://en.wikipedia.org/wiki/MIPS_instruction_set

• Hennessey and Patterson describe three implementations of the

MIPS Instruction Set Architecture (ISA):
1. Single-cycle
• All instructions are fetched/decoded/executed in a single clock cycle.
• The length of the clock cycle is determined by the time required to
process the longest instruction (in the ISA).

• The single-cycle implementation is covered in the lab.

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MIPS (Single-cycle)

“Computer Organization and Design”, 5th Edition; Hennessey and Patterson; p. 265
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MIPS
2. Multi-cycle
• Instruction processing is divided into steps (or stages).
• Each step (or stage) requires one clock cycle.
• The length of the clock cycle is determined by the time required to
complete the longest step in the instruction processing.
• Different instructions require a different number and set of steps.
• Different instructions require a different amount of time.
• Uses the datapath more efficiently than the single-cycle implementation.

• The multi-cycle implementation will be used as the example processor

when discussing control unit design.
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MIPS (Multi-cycle)

“Computer Organization and Design”, 3rd Edition; Hennessey and Patterson; p. 323
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MIPS
3. Pipelined
• Instruction processing is divided into steps (or stages).
• Each step (or stage) requires one clock cycle.
• The length of the clock cycle is determined by the time required to
complete the longest step in the instruction processing.
• Overlap the execution of multiple instructions, such that each instruction
is at a different stage of processing.
• All instructions must pass through every stage of the pipeline.
• All instructions require the same amount of time.

• The pipelined implementation will be discussed at length in later lectures.

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MIPS (Pipelined)

“Computer Organization and Design”, 5th Edition; Hennessey and Patterson; p. 304
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MIPS
• I have designed a fourth implementation of the MIPS ISA:

4. One-bus
• Instruction processing is divided into steps (or stages).
• Each step (or stage) requires one clock cycle.
• The length of the clock cycle is determined by the time required to
complete the longest step in the instruction processing.
• Different instructions require a different number and set of steps.
• Different instructions require a different amount of time.

• The One-bus implementation will be developed and discussed in detail.

• Like the multi-cycle implementation, the One-bus implementation
fetches, decodes, and executes each instruction in multiple clock cycles.
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MIPS (One-bus)
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Questions?
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ADDITIONAL SLIDES
Register Transfer Notation (RTN)
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Register Transfer Notation (RTN)

• Provides a formal means of describing the structure and
function of a digital system.
• It does not replace a hardware description language.

• Abstract RTN
• Can be used to describe what a digital system does without describing
how the digital system does it. (Description of the architecture).
• Concrete RTN
• Can be used to describe a specific hardware implementation.
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Describing Registers
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Describing Registers
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Describing Micro-operations
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Describing Memory
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Naming Fields of Instruction Formats