CME 4456

RECONFIGURABLE COMPUTING

VHDL

Şerife YILMAZ 1
 Languages Other Than VHDL

 VHDL: VHSIC (Very High Speed

Integrated Circuit) Hardware Description
Language
– Not the only hardware description language

2
 ABEL

 ABEL
– Simplified HDL
– PLD language
– Dataflow primitives, e.g., registers
– Program XILINX FPGA

3
 ALTERA

 ALTERA
– Created by Altera Corporation
– Simplified dialect of HDL

4
 AHPL

 AHPL: A Hardware Programming

Language
– Dataflow language
– Implicit clock
– Does not support asynchronous circuits
– Fixed data types
– Non-hierarchical

5
 CDL

 CDL: Computer Design Language

– Academic language for teaching digital systems
– Dataflow language
– Non-hierarchical
– Contains conditional statements

6
 CONLAN

 CONLAN: CONsensus LANguage

– Family of languages for describing various
levels of abstraction
– Concurrent
– Hierarchical

7
 IDL

 IDL: Interactive Design Language

– Internal IBM language
– Originally for automatic generation of PLA
structures
– Generalized to cover other circuits
– Concurrent
– Hierarchical

8
 ISPS

 ISPS: Instruction Set Processor

Specification
– Behavioral language
– Used to design software based on specific
hardware
– Statement level timing control, but no gate
level control

9
 TEGAS

 TEGAS: TEst Generation And Simulation

– Structural with behavioral extensions
– Hierarchical
– Allows detailed timing specifications

10
 TI-HDL

 TI-HDL: Texas Instruments Hardware

Description Language
– Created at Texas Instruments
– Hierarchical
– Models synchronous and asynchronous circuits
– Non-extendable fixed data types

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 VERILOG

 Verilog
– Essentially identical in function to VHDL
– Simpler and syntactically different
– Gateway Design Automation
– Early de facto standard for ASIC programming
– Open Verilog International standard
– Programming language interface to allow
connection to non-Verilog code
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 ZEUS

 ZEUS
– Created at General Electric
– Hierarchical
– Functional Descriptions
– Structural Descriptions
– Clock timing, but no gate delays
– No asynchronous circuits

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 Different Representation Models

 Not Mutually Exclusive Models

– Behavioral
– Dataflow
– Structural
– Physical

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 Behavioral Model

 Describes the Function and Timing of

Hardware Independent of Any Specific
Implementation
– Can exist at multiple levels of abstraction,
depending on the granularity of the timing and
the data types that are used in the functional
description

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 Dataflow Model

 Describes How Data Moves Through the

System and the Various Processing Steps
– Register Transfer Level (RTL)
– No registers are native to VHDL
– Hides details of underlying combinational
circuitry

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 Structural Model

 Represents a System in Terms of the

Interconnections of a Set of Components
– Components are described structurally or
behaviorally, with interfaces between structural
and behavioral-level models

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 Physical Model

 Specifies the Relationship Between the

Component Model and the Physical
Packaging of the Component.
– Contains all the timing and performance details
to allow for an accurate simulation of physical
reality

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 Outline
 VHDL Background/History
 VHDL Design Example
 VHDL Model Components
– Entity Declarations
– Architecture Descriptions
 Basic Syntax and Lexigraphical
Conventions
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Copyright  1997, KJH

 Reasons for Using VHDL

 VHDL Is an International IEEE Standard

Specification Language (IEEE 1076-1993)
for Describing Digital Hardware Used by
Industry Worldwide
– VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware
Description Language
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Copyright  1995, 1996 RASSP E&F

 Reasons for Using VHDL

 VHDL enables hardware modeling from the

gate to system level
 VHDL provides a mechanism for digital
design and reusable design documentation

 VHDL Provides a Common

Communications Medium
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 A Brief History of VHDL
 Very
High Speed Integrated Circuit
(VHSIC) Program
– Launched in 1980
– Object was to achieve significant gains in
VLSI technology by shortening the time from
concept to implementation (18 months to 6
months)
– Need for common descriptive language

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 A Brief History of VHDL

 Woods Hole Workshop

– Held in June 1981 in Massachusetts
– Discussion of VHSIC goals
– Comprised of members of industry,
government, and academia

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 A Brief History of VHDL

 July
1983: contract awarded to develop
VHDL
– Intermetrics
– IBM
– Texas Instruments
 August 1985: VHDL Version 7.2 released

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 A Brief History of VHDL

 December 1987: VHDL became IEEE

Standard 1076-1987 and in 1988 an ANSI
standard
 September 1993: VHDL was restandardized
to clarify and enhance the language
 VHDL-2001 : IEEE Standard 1076.6,

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 Revisions
 IEEE 1076-1987 First standardized revision of ver 7.2 of the language from the
United States Air Force.
 IEEE 1076-1993 (also published with ISBN 1-55937-376-8). Significant
improvements resulting from several years of feedback. Probably the most widely
used version with the greatest vendor tool support.
 IEEE 1076-2000. Minor revision. Introduces the use of protected types.
 IEEE 1076-2002. Minor revision of 1076-2000. Rules with regard to buffer ports
are relaxed.
 IEC 61691-1-1:2004. IEC adoption of IEEE 1076-2002.
 IEEE 1076-2008 (previously referred to as 1076-200x). Major revision released on
2009-01-26. Among other changes, this standard incorporates a basic subset of
PSL, allows for generics on packages and subprograms and introduces the use of
external names.
 IEC 61691-1-1:2011. IEC adoption of IEEE 1076-2008.
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 Related standards
 IEEE 1076.1 VHDL Analog and Mixed-Signal (VHDL-AMS)
 IEEE 1076.1.1 VHDL-AMS Standard Packages (stdpkgs)
 IEEE 1076.2 VHDL Math Package
 IEEE 1076.3 VHDL Synthesis Package (vhdlsynth) (numeric_std)
 IEEE 1076.3 VHDL Synthesis Package – Floating Point (fphdl)
 IEEE 1076.4 Timing (VHDL Initiative Towards ASIC Libraries:
vital)
 IEEE 1076.6 VHDL Synthesis Interoperability (withdrawn in
2010)[11]
 IEEE 1164 VHDL Multivalue Logic (std_logic_1164) Packages
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 Gajski and Kuhn’s Y Chart
Architectural Structural
Behavioral
Algorithmic
Processor
Functional Block
Systems Hardware Modules
Algorithms Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transfer Functions Transistors

Rectangles

Cell, Module Plans

Floor Plans

Clusters

Physical Partitions

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Physical/Geometry
Copyright  1995, 1996 RASSP E&F
 VHDL Model
Package

Generic Ports
Entity

Behavioral Dataflow Structural

Architect Architect Architect

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 VHDL Design Example
 Problem: Design a single bit half adder with carry and enable
 Specifications
– Inputs and outputs are each one bit
– When enable is high, result gets x plus y
– When enable is high, carry gets any carry of x plus y
– Outputs are zero when enable input is low

x
carry
y Half Adder
result
enable
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Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Entity Declaration

 As a first step, the entity declaration describes

the interface of the component
– input and output ports are declared

ENTITY half_adder IS

PORT( x, y, enable: IN BIT;

carry, result: OUT BIT);

END half_adder;

x
Half carry
y
Adder result
enable 31

Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Behavioral Specification

 A high level description can be used to describe the

function of the adder
ARCHITECTURE half_adder_a OF half_adder IS
BEGIN
PROCESS (x, y, enable)
BEGIN
IF enable = ‘1’ THEN
result <= x XOR y;
carry <= x AND y;
ELSE
carry <= ‘0’;
result <= ‘0’;
END IF;
END PROCESS;
END half_adder_a;

 The model can then be simulated to verify

correct functionality of the component 32

Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Data Flow Specification

A Second Method Is to Use Logic Equations to

Develop a Data Flow Description

ARCHITECTURE half_adder_b OF half_adder IS

BEGIN
carry <= enable AND (x AND y);
result <= enable AND (x XOR y);
END half_adder_b;

 Again, the model can be simulated at this level to

confirm the logic equations
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Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Structural Specification

 As a Third Method, a Structural Description Can Be Created

From Previously Described Components

x
y carry
enable
result

 These gates can be pulled from a library of parts

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Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Structural Specification (Cont.)
ARCHITECTURE half_adder_c OF half_adder IS

COMPONENT and2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;

COMPONENT and3
PORT (in0, in1, in2 : IN BIT;
out0 : OUT BIT);
END COMPONENT;

COMPONENT xor2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;

FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);

FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);

-- description is continued on next slide 35

Copyright  1995, 1996 RASSP E&F

 VHDL Design Example
Structural Specification (Cont.)

-- continuing half_adder_c description

SIGNAL xor_res : BIT; -- internal signal

-- Note that other signals are already declared in entity

BEGIN

A0 : and2 PORT MAP (enable, xor_res, result);

A1 : and3 PORT MAP (x, y, enable, carry);
X0 : xor2 PORT MAP (x, y, xor_res);

END half_adder_c;

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Copyright  1995, 1996 RASSP E&F

 VHDL Model Components
 A Complete VHDL Component Description
Requires a VHDL Entity and a VHDL
Architecture
– The entity defines a component’s interface
– The architecture defines a component’s function

 Several Alternative Architectures May Be

Developed for Use With the Same Entity

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 VHDL Model Components

 Three Areas of Description for a VHDL

Component:
– Structural descriptions
– Behavioral descriptions
– Timing and delay descriptions

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 Process

 Fundamental Unit for Component Behavior

Description Is the Process
– Processes may be explicitly or implicitly
defined and are packaged in architectures

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 VHDL Model Components
 Primary Communication Mechanism Is the
Signal
– Process executions result in new values being
assigned to signals which are then accessible to
other processes
– Similarly, a signal may be accessed by a process
in another architecture by connecting the signal
to ports in the the entities associated with the two
architectures
Output
Output <=
<= My_id
My_id ++ 10;
10; 40
 Entity Declarations

 The Primary Purpose of the Entity Is to

Declare the Signals in the Component’s
Interface
– The interface signals are listed in the PORT
clause
» In this respect, the entity is similar to the schematic
symbol for the component

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Copyright  1995, 1996 RASSP E&F

 Entity Example

x
Half carry
y result
Adder
enable
ENTITY half_adder IS
GENERIC(prop_delay : TIME := 10 ns);
PORT( x, y, enable : IN BIT;
carry, result : OUT BIT);
END half_adder;

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 Entity Declarations
Port Clause

 PORT clause declares the interface signals of the object to the outside
world

 Three parts of the PORT clause

PORT
PORT (signal_name
(signal_name :: mode
mode data_type);
data_type);
– Name
– Mode
– Data type

– Note port signals (i.e. ‘ports’) of the same mode and type or subtype may be
declared on the same line
PORT
PORT (( input
input :: IN
IN BIT_VECTOR(3
BIT_VECTOR(3 DOWNTO
DOWNTO 0);
0);
ready,
ready, output
output :: OUT
OUT BIT
BIT );
); 43

Copyright  1995, 1996 RASSP E&F

 Entity Declarations
Port Clause (Cont.)

 The Port Mode of the Interface Describes the

Direction in Which Data Travels With Respect to
the Component
 Five Port Modes

1. In: data comes in this port and can only be read

2. Out: data travels out this port

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 Entity Declarations
Port Clause (Cont.)

3. Buffer: bidirectional data, but only one

signal driver may be enabled at any one time

4. Inout: bidirectional data with any number of

active drivers allowed but requires a Bus
Resolution Function

5. Linkage: direction of data is unknown

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 Entity Declarations
Generic Clause

 Generics May Be Used for Readability,

Maintenance and Configuration
 Generic Clause Syntax :
GENERIC
GENERIC (generic_name
(generic_name :: type
type [:=
[:= default_value]);
default_value]);

– If optional default_value missing in

generic clause declaration, it must be present
when component is to be used (i.e. instantiated)

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Copyright  1995, 1996 RASSP E&F

 Generic Clause

 Generic Clause Example :

GENERIC
GENERIC (My_ID
(My_ID :: INTEGER
INTEGER :=
:= 37);
37);

– The generic My_ID, with a default value of 37,

can be referenced by any architecture of the
entity with this generic clause
– The default can be overridden at component
instantiation

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 Architecture Bodies

 Describes the Operation of the Component,

Not Just Its Interface

 MoreThan One Architecture Can (and

Usually Is) Associated With Each Entity

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 Architecture Bodies

 Consist of Two Parts:

1. Declarative part -- includes necessary
declarations, e.g. :
» type declarations
» signal declarations
» component declarations
» subprogram declarations

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 Architecture Bodies

2. Statement part -- includes statements that

describe organization and/or functional
operation of component, e.g. :
» concurrent signal assignment statements
» process statements
» component instantiation statements

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 Architecture Body, e.g.
ARCHITECTURE half_adder_d OF half_adder
IS
-- architecture declarative part
SIGNAL xor_res : BIT ;
-- architecture statement part
BEGIN
carry <= enable AND (x AND y) ;
result <= enable AND xor_res ;
xor_res <= x XOR y ;
END half_adder_d ;

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 Structural Descriptions

 Pre-Defined VHDL Components Are

‘Instantiated’ and Connected Together

 Structural Descriptions May Connect

Simple Gates or Complex, Abstract
Components

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 Structural Descriptions

 Mechanisms for Supporting Hierarchical

Description

 Mechanisms for Describing Highly

Repetitive Structures Easily
Input Behavioral Output
Entity

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Copyright  1995, 1996 RASSP E&F

 Behavioral Descriptions

 VHDL Provides Two Styles of Describing

Component Behavior
– Data Flow: concurrent signal assignment statements
– Behavioral: processes used to describe complex
behavior by means of high-level language constructs
» variables, loops, if-then-else statements, etc.

54

Copyright  1995, 1996 RASSP E&F

 Behavioral Descriptions

 A Behavioral Model May Bear Little

Resemblance to System Implementation
– Structure not necessarily implied

Input Behavioral Output

Description

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 Lexical Elements of VHDL

 Comments
– two dashes to end of line is a comment, e.g.,

--this is a comment

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Copyright  1997, KJH

 Lexical Elements of VHDL

 Basic Identifiers
– Can Only Use
» alphabetic letters ( A-Z, a-z ), or
» Decimal digits ( 0-9 ), or
» Underline character ( _ )
– Must Start With Alphabetic Letter ( MyVal )

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Copyright  1997, KJH

 Lexical Elements of VHDL

 Basic Identifiers
– Not case sensitive
( LastValue = = lAsTvALue)
– May NOT end with underline ( MyVal_ )
– May NOT contain sequential underlines
(My__Val)

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Copyright  1997, KJH

 Lexical Elements of VHDL

 Extended Identifiers
– Any character(s) enclosed by \ \
– Case IS significant
– Extended identifiers are distinct from basic
identifiers
– If “ \ ” is needed in extended identifier, use
“ \\ “

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Copyright  1997, KJH

 Lexical Elements of VHDL

 Reserved Words
– Do not use as identifiers
 Special Symbols
– Single characters
& ‘ ( ) * + , - . / : ; < = > |
– Double characters (no intervening space)
=> ** := /= >= <= <>
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 Lexical Elements of VHDL
 Numbers
– Underlines are NOT significant
( 10#8_192 )
– Exponential notation allowed
( 46e5 , 98.6E+12 )
– Integer Literals ( 12 )
» Only positive numbers; negative numbers are preceded by
unary negation operator
» No radix point

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Copyright  1997, KJH

 Lexical Elements of VHDL

– Real Literals ( 23.1 )

» Always include decimal point
» Radix point must be preceded and followed by at
least one digit.
– Radix ( radix # number expressed in radix)
» Any radix from binary ( 2 ) to hexadecimal ( 16 )
» Numbers in radices > 10 use letters a-f for 10-15.

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 Lexical Elements of VHDL
 String
– A sequence of any printable characters enclosed in
double quotes
( “a string” )
– Quote uses double quote
( “ he said ““no!”” “)
– Strings longer than one line use the concatenation
operator ( & ) at beginning of continuation line.
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Copyright  1997, KJH

 Lexical Elements of VHDL

 Characters
– Any printable character including space
enclosed in single quotes ( ‘x‘ )
 Bit Strings
– B for binary ( b”0100_1001” )
– O for Octal ( o”76443” )
– X for hexadecimal ( x”FFFE_F138” )

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 VHDL Syntax

 Extended Backus-Naur Form (EBNF)

– Language divided into syntactic categories
– Each category has a rule describing how to
build a rule of that category
– Syntactic category <= pattern
– “<=“ is read as “...is defined to be...”

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Copyright  1997, KJH

 VHDL Syntax

– e.g.,
variable_assignment <= target :=
expression;
– A clause of the category variable_assignment is
defined to be a clause from the category target
followed by the symbol “ := “ followed by a
clause from the expression category followed
by a terminating “ ; ”

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 VHDL Syntax

– syntax between outline brackets [ ] is optional

– syntax between outline braces { } can be

repeated none or more times, aka “Kleene Star”

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Copyright  1997, KJH

 VHDL Syntax

– A preceding lexical element can be repeated an

arbitrary number of times if ellipses are present,
e.g.,
case-statement <=
case expression is
case_statement_alternative
{ . . . }
end case ;

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Copyright  1997, KJH

 VHDL Syntax

– If a delimiter is needed, it is included with the

ellipses as

identifier_list <=
identifier { , . . . }

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Copyright  1997, KJH

 VHDL Syntax

 “OR” operator, “ | ”, in a list of alternatives,

e.g.,
mode <= in | out | inout
 When grouping is ambiguous, parenthesis
are used, e.g.,
term <=
factor { ( * | / | mod | rem ) factor }

70

Copyright  1997, KJH

 VHDL Syntax

 e.g. an identifier may be defined in EBNF as

identifier <=
letter { [ underline ] letter_or_digit }

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 VHDL Lecture 1

 The end...

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