CLOCK SKEW
VLSI Design and ECE
Dr. B. R. Ambedkar National Institute of Technology
Jalandhar
Submitted To: Submitted By:
Dr. Mamta Khosla 1. Prajjwal Shukla (20204107) (VLSI)
Associate Professor 2. Shivali (20904119) (VLSI)
NIT Jalandhar 3. Harshit Kumar (20204007) (ECE)
4. Shefali Sharma (20204019) (ECE)
5. Esha Agarwal (20904031) (ECE)
Clock Skew
Clock skew (sometimes called timing skew) is a phenomenon
in synchronous digital circuit systems (such as computer systems) in
which the same sourced clock signal arrives at
different components at different times. The instantaneous difference
between the readings of any two clocks is called their skew.
In Digital Circuit Design a “ Sequentially Adjacent ” circuit is one
where if a pulse emitted from a common source is supposed to arrive
at the same time. Using this definition we can write a mathematical
expression for
Ta(Time of arrival of cluck pulse at component a)
Tb(Time of arrival of cluck pulse at component b)
Then,
Clock skew Ts = Ta - Tb
Causes of clock skew
Wire-interconnect length
Temperature variations
Capacitive coupling
Material imperfections and
Differences in input capacitance on the clock inputs
Difference between arrival time of the clock
at different devices
Timing Diagram of Clock Skew
Positive Skew and Negative Skew
POSITIVE SKEW NEGATIVE SKEW
When both data and clock are When both data and clock are
travelling in same direction. travelling in opposite direction.
Positive Skew:
Timing Diagram of Positive Skew
Negative Skew
Timing Diagram of Negative Skew
Set Up and Hold Time
Set Up Time-
It is defined as the minimum amount
of time BEFORE the clock's active edge
by which the data must be stable for it to
be latched correctly.
Hold time-
It is defined as the minimum amount of
time after the clock's active edge during
which data must be stable
Set Up and Hold Conditions
No Clock Skew
Tcq + Tcombo = TA
Tcq - Tsetup = TR
TR : Required Time
TA : Arrival Time
With Clock Skew
TA>TR
Violation
TA<TR
Good condition for setup
TA> Hold time
Set Up Analysis
Set Up Analysis Equation:
Tcq + Tcombo < Tclk – Tsetup + Tskew
Hold Analysis
Hold Analysis Equation:
Tcq + TA > Thold + Tskew
To Avoid Set Up Time Violations
The combinational logic between the flip-flops should be
optimized to get minimum delay.
Redesign the flip-flops to get lesser setup time.
Play with clock skew (useful skews).
To Avoid Hold Time Violations
One can add lockup-latches (in cases where the hold time
requirement is very huge, basically to avoid data slip).
By adding delays (using buffers).
Methods to minimize clock skew
Adding Delay in Data Path: The amount of the inserted delay in
the data path should be large enough so that the data path delay
becomes sufficiently greater than the clock skew.
Clock Reversing: In this technique Clock is applied in the reverse
direction with respect to data so that clock skew is automatically
eliminated.
Alternate Phase Clocking:
a) Clocking on Alternate Edges:
In this method, sequentially adjacent Flops are clocked on
the opposite edges of the clock.
b) Clocking on Alternate Phases:
A set of adjacent Flops, which are alternately clocked on two
different phases of the same clock. In this case, between each two
adjacent Flops, there is a safety margin approximately equal to
the phase difference of the two phases.
c) Ripple Clocking Structure:
In a ripple structure, each Flop output drives the next Flop clock
port just like the way a Ripple counter is implemented. Here the
sink Flop will not clock unless the source Flop toggled. This will
eliminate the clock skew since the Flops do not toggle on the
same clock.
Balancing Trace Length:
Apart from merely providing equal traces on all clock nets, the
same termination strategy should be used on each trace by
placing the same load at the end of the line. This would make
sure trace lengths are properly balanced.
Example
Txy= Network delay from X to Y
Txd= Network delay from X to D
Tqy= Network delay from Q to Y
Tqd= Network delay from Q to D
Circuit 1
Minimum Clock Period
Tw ≥ [Link] + [Link] + (n-2) [Link] + [Link] + tsu
Tw ≥ [Link] + [Link] + tsd
Maximum Delay
Tcy ≤ [Link] + [Link] + (n-1) [Link]
Minimum Delay
Tcy ≥ [Link] + [Link]
Circuit 2
Minimum Clock Delay
Tw ≥ [Link] + [Link] + tsu
Tw ≥ [Link] + [Link] + tsu
Maximum Delay
Tcy ≤ [Link] + Max.([Link] , [Link])
Minimum Delay
Tcy ≥ [Link] + Min.([Link] , [Link])
Thank You
