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Lecture 15

This document discusses combinational logic circuits including exclusive OR (XOR) and equivalence functions. It provides truth tables and logic diagrams for 2-input and 3-input XOR gates. It also describes how XOR functions can be used for parity generation and checking in error detection. Specifically, it provides the logic diagrams and truth tables for 3-bit even and odd parity generators as well as a 4-bit even parity checker and derives the circuit for a 3-bit odd parity generator and checker.

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58 views

Lecture 15

This document discusses combinational logic circuits including exclusive OR (XOR) and equivalence functions. It provides truth tables and logic diagrams for 2-input and 3-input XOR gates. It also describes how XOR functions can be used for parity generation and checking in error detection. Specifically, it provides the logic diagrams and truth tables for 3-bit even and odd parity generators as well as a 4-bit even parity checker and derives the circuit for a 3-bit odd parity generator and checker.

Uploaded by

muktikanta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Combinational Logic

Overview of previous Lecture

Simplification of Boolean functions using Map


method ( Two and Three variable map methods)
SOP & POS implementation using NAND & NOR
gates.
Exclusive OR and Equivalence Functions
 The exclusive-OR (XOR), denoted by the symbol ,is a logical
operation that performs the following Boolean operation:

It is particularly useful in arithmetic operations and error


detection and correction circuits.

The exclusive-OR is equal to 1 if only x is equal to 1 or if only y


is equal to 1 (i.e., x and y differ in value), but not when both are
equal to 1 or when both are equal to 0. The exclusive NOR, also
known as equivalence, performs the following Boolean operation:
 The exclusive-NOR is equal to 1 if both x and y are equal to 1 or
if both are equal to 0. The exclusive-NOR can be shown to be the
complement of the exclusive-OR by means of a truth table or by
algebraic manipulation:

 The following identities apply to the exclusive-OR operation:


 Also, it can be shown that the exclusive-OR operation
is both commutative and associative; that is,

This means that the two inputs to an exclusive-OR gate can be


interchanged without affecting the operation.

 Hence there is the possibility of using exclusive-OR gates with


three or more inputs.
Construction of a two-input exclusive-OR function:

Exclusive-OR implementations
HDL for XOR gate

// Verilog model for XOR gate.


module exclusiveor-df (F, x, y);
output F;
input x, y;
assign F = (x && (!y)) || ((!x) && y);
endmodule
Odd Function
The exclusive-OR operation with three or more variables can be
converted into an ordinary Boolean function by replacing the
symbol with its equivalent Boolean expression. In particular,
the three-variable case can be converted to a Boolean expression
as follows:

The multiple-variable exclusive-OR operation is defined as an


odd function because in the case of three or more variables the
requirement is that an odd number of variables be equal to 1.
 In general, an n -variable exclusive-OR function is an
odd function defined as the logical sum of the 2n/2
minterms whose binary numerical values have an odd
number of 1’s.
The definition of an odd function can be clarified by
plotting it in a map.

Map for a three-variable exclusive-OR function


Logic diagram of odd and even functions

The three-input odd function is implemented by means of


two-input exclusive-OR gates, as shown in Fig (a). The
complement of an odd function is obtained by replacing the
output gate with an exclusive-NOR gate, as shown in Fig.(b).
 Consider now the four-variable exclusive-OR operation. By
algebraic manipulation, we can obtain the sum of minterms for
this function:

There are 16 minterms for a four-variable Boolean function.


Half of the minterms have binary numerical values with an odd
number of 1’s; the other half of the minterms have binary
numerical values with an even number of 1’s.
 In plotting the function in the map, the binary numerical value for a
minterm is determined from the row and column numbers of the
square that represents the minterm.

The map of Fig.(a) is a plot of the 4-variable exclusive-OR function.


This is an odd function because the binary values of all the minterms
have an odd number of 1’s. The complement of an odd function is an
even function. As shown in Fig.(b),the 4-variable even function is
equal to 1 when an even number of its variables is equal to 1.
Parity Generation and Checking

The circuit that generates the parity bit in the


transmitter is called a parity generator.

The circuit that checks the parity in the receiver is


called a parity checker.

Let us consider a three-bit message to be


transmitted together with an even-parity bit.
3-bit even parity generator

Even-Parity-Generator Truth Table


HDL for Even-Parity-Generator Truth Table

// Verilog model: User-defined Primitive


primitive UDP_3 bit evenparity (P, x, y,z);
output P;
input x, y, z;
table
// x y z : P // Column header comment
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 0;
1 1 1 : 1; // Verilog model: Circuit instantiation of Circuit_UDP_02467
endtable module Circuit_with_evenparity (P, x, y, z);
Endprimitive output P;
input x, y, z;
UDP_3 bit evenparity (P, x, y,z);
endmodule
4-bit even parity checker
Even-Parity-Checker Truth Table
HDL for Even-Parity-Checker Circuit

w1

// Verilog model 4 bits even parity checker.


module even-paritychecker-gf (C, x, y, z,
P);
output C;
input x, y, z, P; w2
Wire w1, w2;
xor G1 (w1, x, y),
G2 (w2, z, P),
G3 (C, w1, w2);
endmodule
Example

Show that the dual of the exclusive-OR is also its complement.

Expression of XOR Gate is :

To find the Dual of an expression, change the '.' sign with '+'


and '+' sign with '.', we can also apply De-Morgan's Theorem.
So, Dual of the expression of XOR gate is:
From the Truth Table that I have given, it is clear
that (ii) is the complement of (i).
Derive the circuits for a three-bit parity generator
and four-bit parity checker using an odd parity bit.

3-bit Odd Parity Generator

Suppose at the transmitting end now we have a 3-bit message


signal, and we wish to transmit it using odd parity. Then, the
parity bit generated, P, would be as a result of odd parity
generation. The total number of 1s in the input bits must be odd
for the odd parity bit. If the total number of 1s in input bits is
odd, then P gets the value 0, and if it is even then, P is assigned
the value 1.
3-bit Odd Parity Generator truth table
Solving the truth table for all the cases where P is 1
using Sum-of-Products method:

3-bit Odd Parity Generator circuit


3 Bit Odd Parity Checker
 
 Suppose at the transmitting end odd parity bit is generated, and
we have three input message signal. The parity checker circuit is
fed all these four bits to check for possible errors. Since the
transmitting end is working with odd parity, the number of 1’s at
received by the checker circuit must be odd.

 An error occurs on the even number of 1’s at the receiver’s end;


that is, the message signal has become distorted.
3 Bit Odd Parity Checker truth table
If the four-bit received message consists of an odd number of 1
means, no error has occurred. If it contains an even number of 1
means, an error has occurred.
E = (A Ex-NOR B) Ex-NOR (C Ex-NOR D)
3 Bit Odd Parity Checker circuit
THANK YOU

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