Exception Handling

 Exceptions (when things go wrong)

 Things that are not expected
 Things that are not a part of normal
operations
 Exceptions
 Multiple threads with controls
exchanged frequently

Based on Chapter 12, Goodman, James and Miller Karen

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 Exception handling techniques

 What we do if things go wrong?

 Send out bad results
 let it crash
 Try to recover
 How to shift controls between two
regular programs?
 All information must be saved
 Me able to resume normal execution
after shift

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 Exception handling
 Java
 Two classes for modeling problems
• Error
• Exception
 Exception handling
• Raise an exception
• Catch an exception
• Throw an exception
 Multiple threads synchronization

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C
 No forced exception handling
mechanism
 Error no
 Signal handling
• A protocol for two processes to
communicate about errors and exceptions
 Modules developed for exception
handling
 Multiple processes and/ threads

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 Database management systems
 Logs for recording update information
 Check point for periodically enforcing
log writing
 Recovery for recovering the database
into a consistent state after any type of
errors and crash

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 How to detect exceptions?
 Polling
Has to stop working every once in a while to
see if there is someone in need of attention.
 Advantages
• Never interrupted in the middle of a task, thus can
plan when to stop to check.
 Disadvantages
• Will stop working several times to check when there
is nobody there.
• Someone might have to wait for a while until the
next pooling opportunity to be noticed.

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 How to detect exceptions?

 Interruption
When someone needs attention that person
will interrupt the work.
 Advantages
• Never need to stop working if nobody needs
attention.
 Disadvantages
• Will be stopped in the middle of a task. More
difficult to save/restore state (context switching
can be expensive).
• Hardware and software must be involvedto provide
a context switching mechanism.

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 MIPS Exceptions
 Trap
 Synchronous exceptions, resulting directly
from the execution of the program, such as
• Arithmetic overflow
• Out of bond memory access
 Interruption
 Asynchronous exceptions, resulting from
external events, such as
• IO request
• Control shift

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 The MIPS Exception
Mechanism
A MIPS processor operates in one of two modes: kernel and user.
( Kernel can be viewed as the exception handler of the operating system)

When running in the kernel mode, a program has access to an

additional set of registers that are not accessible to a program
running in the user mode.

Memory locations in the upper half of the address space, i.e.

memory locations whose most significant bit is 1, can only be
accessed in the kernel mode.

This region include:

- Exception handler code
- Data that is only accessible by the operating system
- Memory-mapped I/O addresses

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 Co-processor C0

Co-processor C0 only can

be accessed when executing
in the kernel mode.

The registers of coprocessor

C0 are accessed, when
executing in the kernel mode,
through the instructions
mtc0 and mfc0

Exception Program Counter

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 CP0 Registers

Register Name Reg. Number

Context 4
BadVAddr (Bad Virtual Address) 8
Count 9
Compare register 11
Status 12
Cause 13
EPC (Exception Program Counter) 14
WatchLo (Mem. Ref. Trap Addr. Low) 18
WatchHi (Mem. Ref. Trap Addr. High) 19
Xcontext 20
ECC 26
CacheErr (Cache Error Status) 27
ErrorEPC (Erroe Except. Prog. Counter) 30

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 The Cause Register

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0

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 The Cause Register

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0

Exception Mnemonic Meaning

Code
0 Int Interruption
1-3 TLB exceptions
4 AdEL Address error exception (load)
5 AdES Address error exception (store)
6 IBE Bus error on instruction fetch
7 DBE Bus error on data reference
8 Sys Syscall instruction
9 Break Break instruction
10 RI Reserved
11 CpU Co-processor unusable
12 Ov Arithmetic overflow
13 Tr Trap Exception
15 FPE Floating Point Exception
16-31 (future use)
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 The Cause Register

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0

External Software
Interrupts Interrupts

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
CU: 4 bits to control co-processor usability

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
CU: 4 bits to control co-processor usability

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
CU: 4 bits to control co-processor usability

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
CU: 4 bits to control co-processor usability

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
CU: 4 bits to control co-processor usability

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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
RP: Enables reduced-power operation (reduce clock freq.)
CU: 4 bits to control co-processor usability
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 The Status Register

31-28 27 26 25 24-16 15 14 13 12 11 10 9 8 7-6 5 4 3 2 1 0

CU RP FR RE ••• IM(7) IM(6) IM(5) IM(4) IM(3) IM(2) IM(1) IM(0) ••• KUo IEo PUp IEp KUc IEc

External Software
Interrupts Interrupts

KUc: Is the program running in kernel mode or user mode?

PUp: Was the processor in kernel or user mode when the
last exception occurred?
IM(0)-IM(7): Interrupt Mask. It controls which interrupts are
enabled.
RE: Reverse-Endian (RE) bit. Reverses the endianess of the
machine.
FR: Enables additional floating point registers
RP: Enables reduced-power operation (reduce clock freq.)
CU: 4 bits to control co-processor usability
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Invocation and Return from
the Exception Handler

The MIPS architecture fix a single address --- 0x8000 0080 --- to be
the starting address of the exception handler.

When an exception is invoked, control is transferred to this location.

The exception invocation must also save the returning address for
the exception. But it cannot save this address in $ra, because $ra
contains the returning address for the routine that is currently executing.

The Exception Program Counter (EPC) is loaded with the address at

which processing resumes after an exception is serviced.

The (EPC) is a register of the co-processor C0. The content of the

EPC can be transferred to a general register using the instruction:

mfc0 $ri, $14

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 Exception Handling
Save registers

Load Cause Register

ExecCode?

HandleInterrupt
HandleSyscall

HandleOverflow
Restore registers

Load EPC into $k0

Clean Up State

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Examining the Exception Code
Exception Handler:
<preliminary check for reentrance>
OK: <set flag>
<save registers>
mfc0 $k0, $13 # Get the Cause Register
andi $k0, $k0, $0x7c # Mask out the ExcCode bits
lw $k0, JumpTable($k0) # Read address from jump table
jr $k0 # Jump to exception handler

$k0 = bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb

AND 0x7c = 0000 0000 0000 0000 0000 0000 0111 1100
$k0 = 0000 0000 0000 0000 0000 0000 0bbb bb00

31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0

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Examining the Exception Code
Exception Handler:
<preliminary check for reentrance>
OK: <set flag>
<save registers>
mfc0 $k0, $13 # Get the Cause Register
andi $k0, $k0, $0x7c # Mask out the ExcCode bits
lw $k0, JumpTable($k0) # Read address from jump table
jr $k0 # Jump to exception handler
Return: <restore registers>
<clear flag>
mfc0 $k0, $14 # Get EPC register
rfe # clean up state register
jr $k0 # return to the address in EPC

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 Building the Jump Table
(The Cause Register)
31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BD 0 CE 0•••0 IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) IP(1) IP(0) 0 ExcCode 0 0

Exception Mnemonic Meaning

Code
0 Int Interruption
1-3 TLB exceptions
4 AdEL Address error exception (load)
5 AdES Address error exception (store)
6 IBE Bus error on instruction fetch
7 DBE Bus error on data reference
8 Sys Syscall instruction
9 Break Break instruction
10 CpU Co-processor unusable
12 Ov Arithmetic overflow
13 Tr Trap Exception
15 FPE Floating Point Exception
16-31 (future use)
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 Building the Jump Table
Exception Handler:
JumpTable:
.word HandleInt # Interrupt
.word HandleMOD # TLB modification exception
.word HandleTLBL # TLB miss exception (load or fetch)
.word HandleTLBS # TLB miss exception (store)
.word HandleAdEL # Address error exception (load or fetch)
.word HandleAdES # Address error exception (store)
.word HandleIBE # Bus error exception (for a fetch)
.word HandleDBE # Bus error exception (for a load or store)
.word HandleSys # Syscall exception
.word HandleBp # Breakpoint exception
.word HandleRI # Reserved Instruction Exception
.word HandleCpU # Co-processor Unusable exception
.word HandleOvf # Arithmetic overflow exception
.word HandleFPInexact # Inexact floating point result
.word HandleDivideBy0 # Divide by 0
.word HandleFPOvf # FP Overflow
.word HandleFPUnder # FP Underflow
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, CMPUT
HandleRes, HandleRes, HandleRes
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 The Syscall Handle

In this example of exception handling, lets assume that we want

to handle the following syscall functions: putc, puts, exit, and getc.

In order to obtain one of this services, the user’s program must

pass the following codes in $v0:
$v0 syscall service
12 getc
11 putc
10 exit
4 puts

We assume that the value of $v0 was saved at the beginning of

the exception service in the memory location tmpv0

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 The Syscall Handle

Exception Handler:
HandleSys:
mfc0 $k1, $14 # Get the EPC Register
addi $k1, $k1, 4 # Increment PC past syscall instruction
mtc0 $k1, $14 # Set the EPC Register

lw $v0, tmpv0 # get the previously saved value of $v0

li $a0, 11 # Is it putc?
beq $v0, $a0, Putc
li $a0, 4 # Is it puts?
beq $v0, $a0, Puts
li $a0, 12 # Is it getc?
beq $v0, $a0, Getc
li $a0, 10 # Is it exit?
beq $v0, $a0, Exit

la $a0, SysMessage # Bad number in $v0

jal Print String # Print message
j Return

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 The Syscall Handle

Exception Handler:
Exit: <code for Exit>

Putc: <code for Putc>

Puts: <code for Putc>

Getc: <code for Getc>

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 Checking for Reentrance
Exception Handler:
flag: .word 0 # remembers if it was already in the
# exception handler when the exception
# occurred
BadReentry:
.asciiz “Bad re-entry into kernel\nHalting\n”
.ktext
.space 0x80 # skip space so that the handler is at 0x80000080
add $k1, $at, $zero # immediately save $at
lw $k0, flag # SPIM translates this instruction to:
# lui $at, 4097
# lw $k0, 0($at)
beq $k0, $zero, OK
la $a0, BadReentry
j Panic
OK: <set flag>
<save registers>
mfc0 $k0, $13 # Get the Cause Register
andi $k0, $k0, 0x7c # Mask out the ExcCode bits
lw $k0, JumpTable($k0) # Read address from jump table
jr $k0 # Jump to exception handler

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 Code for Panic

The code for Panic has to print the following message:

Panic: Bad re-entry into kernel\nHalting\n

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 Panic
Exception Handler:
DisplayData = 0xbfff0008
DisplayStatus = 0xbfff000c
.kdata
Pmess: .asciiz “Panic: “
.ktext # Panic prints a message and quits

Panic: la $a1, Pmess

PRead1: lb $a2, ($a1) # read letter to print
beq $a2, $zero, PRead2 # done when we find a null
PWait1: lw $a3, DisplayStatus # Read the status of the display
bge $a3,$zero, PWait1 # keep reading until it is ready
sw $a2, DisplayData # output character
addi $a1, $a1, 1 # advance character
j PRead1
PRead2: lb $a2, ($a0) # Print message pointed by $a0
beq $a2, $zero, Pcontinue # done when we find a null
PWait2: lw $a3, DisplayStatus # Read the status of the display
bge $a3, $zero, PWait2 # keep reading until it is ready
sw $a2, DisplayData # output character
addi $a0, $a0, 1 # advance character
j PRead2
Pcontinue: li $v0, 0 # clear re-entrance flag
sw $v0, flag
li $v0, 13 # the quit_now syscall
syscall

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 Save/Restore Registers
Exception Handler:
<preliminary check for reentrance>
OK: <set flag>
<save registers>
mfc0 $k0, $13 # Get the Cause Register
andi $k0, $k0, $0x7c # Mask out the ExcCode bits
lw $k0, JumpTable($k0) # Read address from jump table
jr $k0 # Jump to exception handler

Return: <restore registers>

<clear flag>
mfc0 $k0, $14 # Get EPC register
rfe # clean up state register
jr $k0 # return to the address in EPC

.kdata
tmpat: .word 0
tmpv0: .word 0
tmpa0: .word 0
tmpa1: .word 0
tmpa2: .word 0
tmpa3: .word 0
tmpra: .word 0
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 Save/Restore Registers
.kdata
tmpat: .word 0 # code to save registers
tmpv0: .word 0 sw $k1, tmpat
tmpa0: .word 0 sw $v0, tmpv0
tmpa1: .word 0 sw $a0, tmpa0
tmpa2: .word 0 sw $a1, tmpa1
tmpa3: .word 0 sw $a2, tmpa2
tmpra: .word 0 sw $a3, tmpa3
sw $ra, tmpra

# code to restore registers

lw $v0, tmpv0
lw $a0, tmpa0
lw $a1, tmpa1
lw $a2, tmpa2
lw $a3, tmpa3
lw $ra, tmpra
sw $zero, flag # clear re-entry flag
lw $k1, tmpat # restore $at
add $at, $k1, $zero
mfc0 $k0, $14 # Get EPC register
rfe # clean up state register
jr $k0 # return to the address in EPC
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 Code for Putc
Exception Handler:
.kdata
tmpputra: .word 0
.ktext
Putc: lw $a0, tmpa0
jal Puta0
j Return
Puta0: lw $k0, pqhead # load head of put queue
lw $k1, pqtail # load tail of put queue
addi $k1, 1 # increment tail
andi $k1, $k1, 0x00ff # module counter
beq $k1, $k0, Full # try to print a charn if queue is full
sb $a0, putqueue($k1) # add byte to the queue
sw $k1, pqtail # save new tail
mfc0 $k1, $12 # Get status register
ori $k1, 0x5000 # Turn on display interrupts
mtc0 $k1, $12 # Set status register
sw $ra, tmpputra # Save return address
jal DP_handler # try to print
lw $ra, tmpputra # Restore return address
jr $ra
Full: sw $ra, tmpputra # Save return address
jal DP_handler # Try to print
lw $ra, tmpputra # Restore return address
j Puta0

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 Code for DP_handler

Exception Handler:
.kdata
putqueue: .space 256
.align 2
.ktext
pqtail: .word 0
pqhead: .word 0
.ktext
DP_handler:
lw $k0, DisplayStatus # Get display status word
bge $k0, $zero, DPRet # Return if it is not Ready
lw $k0, pqhead #
lw $k1, pqtail
beq $k0, $k1, DPRet # Return if put queue is empty
addi $k0, $k0, 1 # Increment head
andi $k0, $k0, 0x00ff # Module counter
sw $k0, pqhead # Save new head
lb $k0, putqueue($k0) # get character from put queue
sb $k0, DisplayData # Send character to display
DPRet: jr $ra # Return to caller

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 Code for Puts

Exception Handler:
.kdata
tmpputsra: .word 0
Puts: lw $k0, tmpa0 # Get address of first character
PutsLoop: lbu $a0, ($k0) # Get a character
beq $a0, $zero, PutsRet # If character is null, we are done
sw $ra, tmpputsra # Save return address
jal Puta0 # Print the character
sw $ra, tmpputsra # Save return address
addi $k0, $k0, 1 # Move pointer to next character
j PutsLoop # Loop back
PutsRet: jr $ra

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 Bad Virtual Address Register

The register $8 of the coprocessor 0 is the BadVAddr (Bad Virtual Address)

register. It is a read only address register that contains the most recent
virtual address that caused one of the following exceptions:

TLB Invalid
TLB Modified
TLB Refill
Virtual Coherency Data Access
Virtual Coherency Instruction Fetch

The BadVAddr does not save any information for bus errors, since
bus errors are not addressing errors.

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