CHAPTER FOUR

Memory Organization

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 Outline
 Classification of Memories
 Memory types: RAM, ROM
 Memory Chip Capacity & Organization
 Electrical Signals
 Organization of a Typical memory chips
− RAM
− Reprogrammable ROMs
EPROM
EEPROM

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 Classification of Memories
• Memory in a MP system is where information (data &
instructions) is kept.
• It can be classified in to two main types:
– Main memory (RAM & ROM)
• It is a memory unit that communicate directly with the CPU. Main memories
are fabricated from semiconductors. only programs & data currently needed by
the processor reside in main memory.
– Storage memory (Disks , CD ROMs, etc.)
• Devices that provide backup storage are called secondary (auxiliary ) memory.
These are constructed from magnetized materials
• The simple view of RAM is that it is made up of registers that are
made up of flip-flops (or memory elements).
– The number of flip-flops in a “memory register” determines the size of
the memory word.
• ROM on the other hand uses diodes instead of the flip-flops to
permanently hold the information. 3
 Memory

Primary Memory Secondary Memory

RWM
ROM Disks Tape
(RAM)
MROM

SRAM DRAM
Floppy
PROM
Flash
memory
Bubble H/D
EPROM

EEPROM
(EAROM) Optical

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 Memory hierarchy

• The hierarchy is Registers

Cache
based on the speed, Main memory
Speed

size & distance Electronic Disk

from the processor
Magnetic Disk

Optical Disk
Cost cheap,
Magnetic Tape size

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Semiconductor Technologies for memories
• Bipolar Technology:- high speed
• MOS Technology :- less space (high density), less
power consumption.
PMOS technology –earlier
NMOS technology -speed, density
CMOS technology -less power consumption
(Complementary Metal Oxide Semi-conductor)

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 Types of semiconductor memory
• Semiconductor memories can be classified as:
 Volatile memories –in which information stored is lost when power
supply is off. E.g. RAMs
 Nonvolatile memories– in which information is not lost even when
power is off. E.g. ROMs
• In both RAM & ROM, accessing is random & the memory access time is
independent of the memory location.
 RAM -- allows temporary storage, allows read/write operation,
available in bipolar & MOS technologies:
 Bipolar RAMs– are very fast.
- Access time for TTL RAMs is 20 to 50ns.
- Access time for ECL RAMs is much less---10ns.
 MOS RAMs –access time is 25 to 500ns.
- SRAMs store information in flip-flops.
- DRAMs store information in capacitive stray.
 ROM – allows permanent storage, allows read only operation,
available in bipolar & MOS technologies.
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 Types of ROMs
1. MROM:- Mask-Programmed ROM (MPROM) or simply ROM.
– Programmed by manufacturer according to the customer’s specifications.
The P can only read from such memory. It cannot be reprogrammed
by a user.
– A photographic negative (mask) is used to control the electrical
interconnections on the chip.
2. PROM: Programmable ROM.
It is one time user programmable ROM.
ones it is user programmed it serves as a ROM. i.e. it cannot
reprogrammed again.
both ROM & PROM consists fusible-link in each cell. Blowing off or
retaining the fuse decides whether the cell contains a 1 or a 0.
it is programmed by PROM programmer (apparatus). The Process of
storing information in ROM is called programming or burning the ROM

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3. EPROM: Erasable Programmable ROMs
 can be erased & reprogrammed by user several times.
 it is programmed by EPROM programmer by applying special voltage
levels ( 10 to 25v).
 It is erased by exposing it to UV light applied through a window on the chip.
Disadvantage: - erased/programmed out of chip.
- all cells erased,
- take more time to erase/program(15 to 20min).
Advantage: High density, low cost per bit, high speed, reliable, widely available
UV light

4. EEPROM: Electrically Erasable PROMs (E2PROM or EAROM)

 programmed/erased by applying 21v.
 erased/programmed while under normal operation (in circuit). Thus ideal for
applications where some parametric data needs change over a period of time.
Typical erasure times vary between 1 to 10 sec.
 A cell, unlike EPROM, can be selectively erased/programmed.
Disadvantage: lower density, much costlier than EPROM.
5. Flash memory: it has the best features of both EPROM & EEPROM. It can be
erased either in its entirety or at sector (block ) level.
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 Types of RAMs
1. SRAM: Static RAM
- made up of flip-flops.
- has high speed but low density.
- more expensive, consumes more power than DRAM.
Note: the stored data will remain permanently stored as long as power is
applied
2. DRAM: Dynamic RAM
- it stores the bit as a charge.
- made up of transistor gates.
- it has high density, but low speed.
- low power consumption.
- cheaper than SRAM.
- needs refreshing – requires external circuitry for refreshing, adding cost.
- i.e. the stored data will not remain permanently stored, even with
power applied, unless the data are periodically rewritten (refreshed ) in
to memory.
Note: Both SRAM and DRAM are volatile. 10
 Memory Chip Capacity & Organization
• A memory is a circuit that can store bits—high or low, generally
voltage levels or capacitive charges representing 1 or 0
• The basic memory element is similar to a D latch
• To avoid unintentional change in the input, & control the
availability of the o/p, we can use two tri-state buffers on the latch.
• A latch, which can store one binary bit, is called a memory cell

Memory cell

D IN D OUT
D Q
WR
EN
EN
RD (a) A memory cell latch with
two tri-state Buffers
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 Memory Chip Capacity & Organization…

I7 I0
64kb memory.
• Each register contains 8 D Latch WR Input Buffer
flip-flops.
• The I/P and O/P buffers are each of A0 MR1 0000H

216 =65536
A1 MR2 0001H

Decoder
8 Tri-state buffers.

A14 MR 65535 FFFEH

A15 MR 65536 FFFFH
RD Output Buffer
O7 O0
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• Memory is usually measured by two numbers: its length & its width (Length x Width)
 Capacity of a chip = length x width
 length is total number of words (the total number of locations),
 width is number of bits per word(location).
• Word size is the number of bits a µP can access in parallel at a time.
• The length (total number of words) is a function of the number of address lines
– # of memory locations = 2^( # of address lines)
• So, a memory chip with 10 address lines would have
2^10 = 1024 words or locations (1K)
• Looking at it from the other side, a memory chip with 4K locations would
need log2 4096=12 address lines
 The memory that is addressed by the µP (RAM or ROM) consist of one or more
LSI chips arranged to provide the designed memory capacity.
 Memory capacity for a µP is a memory address range that it can address with its
all address lines.
• The 8085 has 16 address lines. That means it can address
 216 = 65536 bytes = 64kb, Then it will need 1 memory chip with 64 k
locations, or 2 chips with 32K in each, or 4 with 16 K each or 16 of the 4 K
chips, etc. 13
 Organization of some commonly used memory chips
IC No. Make capacity Type Access Time in ns
6116 Hitachi 2kx8-bit SRAM
6132 “ 4kx8-bit SRAM
6264 “ 8kx8-bit RAM (SRAM)
6287 “ 64kx1-bit RAM(SRAM)
2147H Intel 4kx1-bit SRAM 35
21256 “ 256kx1-bit DRAM 60
5164 s/c “ 8kx8-bit CMOS SRAM 35
2716 “ 2kx8-bit EPROM
2764 “ 8kx8-bit EPROM 180

Three cases:
a) Smaller word size chips can be connected to make up an 8-bit word memory.
b) More than one memory chips can be arranged to make up the memory capacity for a µP.
Need of additional chip select (CS) signal- which allows us to expand memory size by
using multiple chips.
c) There are more address lines but less memory chip are sufficient. Two solution:
. Absolute decoding
. Partial decoding– leaving some address lines as don’t care.
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 Chip Select
• Usually, each memory chip has a CS (Chip Select) input. The chip
will only work if an active signal is applied on that input
• To allow the use of multiple chips in the make up of memory, we need
to use a number of the address lines for the purpose of “chip selection”
– These address lines are decoded to generate the necessary CS
inputs for the memory chips to be used.

• Chip Select Example:

• Assume that we need to build a memory system made up of 4 of the 4
X 4 memory chips we designed earlier
• We will need to use 2 inputs and a decoder to identify which chip will
be used at what time
• The resulting design would now look like the one on the following
slide
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