CS305

MICROPROCESSORS AND MICROCONTROLLERS

Vidya Academy of Science & Technology

Department of Computer Science and Engineering
 Signal Description of 8086

CS305 • Intel 8086 was launched in 1978.

• It was the first 16-bit microprocessor.
• This microprocessor had major improvement over the execution
MODULE 1 speed of 8085.
• It is available as 40-pin and Dual-Inline-Package (DIP).
• It is available in three versions:
• 8086 (5 MHz)
• 8086-2 (8 MHz)
• 8086-1 (10 MHz)
• It consists of 29,000 transistors.
• It has a 16 line data bus and 20 line address bus.
• It could address up to 1 MB of memory.
• It has more than 20,000 instructions.
• It supports multiplication and division.
 Signal Description of 8086

CS305

MODULE 1
AD7  AD0

Signal Description of 8086

CS305 8086 signals can be categorized in three groups

• Signals having common functions in minimum as well as maximum
mode.
MODULE 1 • Signals having special functions for minimum mode.
• Signals having special functions for maximum mode.

AD15 – AD0:
• Multiplexed memory I/O address and data lines.
• Address remains on the lines during T1 state, while data is available
on the data bus during T2 ,T3 , Tw and T4.
• T1,T2,T3,T4 and Tw are the clock states of a machine cycle.
• Tw is a wait state.
• These lines are active high and float to a tri-state (high impedance
state) during interrupt acknowledge and local bus acknowledge
cycles.
AD7  AD0

Signal Description of 8086

CS305 A19/S6 ,A18/S5, A17/S4, A16/S3

• Time multiplexed address and status lines.
• During T1 , these are the most significant address lines for memory
MODULE 1 operations.
• During I/O operations, these lines are low.
• During memory or I/O operations, status information is available
on those lines for T2,T3,Tw and T4.
• S6 is always low.
• S5 denotes the status of interrupt enable flag bit and is updated at
the beginning of each clock cycle.
• S4 and S3 together indicate which segment register is presently
being used for memory accesses.
• These lines float to tri-state off during the local bus acknowledge.
• The address bits are separated from the status bits using latches
controlled by the ALE signal.
AD7  AD0

Signal Description of 8086

S4 S3 Indications

0 0 Alternate data
CS305
0 1 Stack
1 0 Code
MODULE 1
1 1 Data

BHE / S7:- Bus High Enable / Status

• Indicate the transfer of data over the higher order (D15 - D8)data.
• It goes low for the data transfers over D15-D8 and is used to derive
chip select of odd address memory bank or peripherals.
• BHE is low during T1 for read ,write and interrupt acknowledge
cycles , whenever a byte is to be transferred on the higher byte of
the data bus.
• The status information is available during T2,T3,and T4.
• Status is active low and is tri-stated during ‘hold’.
AD7  AD0

Signal Description of 8086

BHE A0 Indication
CS305 0 0 Whole word(2 byte)
0 1 Upper byte from or
to odd address
MODULE 1
1 0 Lower byte from or
to even address

1 1 None

RD – Read :-
• Indicates the peripheral that the processor is performing a memory
or I/O operation.
• Active low –T2,T3,Tw of read cycle.
• Tri-stated during hold acknowledge.
READY:-
• Acknowledgement from the slow devices or memory that they
have completed data transfer.
• Signal is active high.
AD7  AD0

Signal Description of 8086

CS305  
INTR:- Interrupt Request
• Sampled during last cycle of each instruction to determine the
MODULE 1 availability of the request.
• If any interrupt request is pending, the processor enters the
interrupt acknowledge cycle.
• Internally marked by resetting the interrupt enable flag.

NMI:-Non Maskable Interrupt

• Causes Type-2 interrupt.
• Not maskable internally by software.
• Transition from low to high initiates the interrupt response at the
end of each instruction.
AD7  AD0

Signal Description of 8086

CS305  
TEST:-
• This input is examined by a WAIT instruction.
MODULE 1 • If the TEST input goes low, execution will continue, else the
processor remains in an idle state.
• It is used to test the status of math coprocessor 8087.

Coprocessor
• 8087 was the first math coprocessor for 16-bit processors
designed by Intel.
• It was built to pair with 8086 and 8088.
• The purpose of 8087 was to speed up the computations involving
floating point calculations.
AD7  AD0

Signal Description of 8086

CS305 • Addition, subtraction, multiplication and division of simple

numbers is not the coprocessor’s job.
• It does all the calculations involving floating point numbers like
MODULE 1 scientific calculations and algebraic functions.
• This increases the overall speed and performance of the entire
system
• The microprocessor and coprocessor can execute their respective
instructions simultaneously.
• Microprocessor interprets and executes the normal instruction set
and the coprocessor interprets and executes only the coprocessor
instructions.
AD7  AD0

Signal Description of 8086

CS305
RESET:-
• Causes the processor to terminate the current activity and start
MODULE 1 execution from FFFFOH.
• Active high for atleast 4 clock cycles.
• Restarts execution when the RESET returns low.

CLK- Clock input:-

• Provide the basic timing for processor operation and bus control
activity.
• Asymmetric square wave with 33% duty cycle.

VCC:- +5 power supply for the operation of the internal circuit.

GND:- ground for the internal circuit.

AD7  AD0

Signal Description of 8086

CS305 Minimum Mode Operation- Pin Function

M / I/O:-
MODULE 1 • Memory I/O (logically equivalent to S2 in maximum mode).
• Low indicates that CPU is having an I/O operation.
MN/MX:- • High indicates that CPU is having a memory operation.
minimum / • Active in the previous T4 and remains active till final T4 of the
maximum
current cycle.
mode
operation .
• Tri-stated during local bus “hold acknowledge”.

INTA:- Interrupt Acknowledge

• Read strobe for interrupt acknowledge cycles.
• Low means processor has accepted the interrupt.
• Active low during T2,T3 and Tw of each interrupt acknowledge
cycle.
AD7  AD0

Signal Description of 8086

ALE:-
CS305 • Indicate the availability of the valid address on address/data lines.
• Connected to latch enable input of latches.
• Active high and is never tri-stated.
MODULE 1

DT/R:- Data Transmit/Receive

• To decide the direction of data flow through transreceivers ( bi-
directional buffers).
• High when processor sends out data.
• Low when processor receives data.
• Tri-stated during ‘hold acknowledge’.

DEN :-Data Enable

• Indicates the availability of valid data over the address/data lines.
• Enable the data transreceivers to separate the data from the
multiplexed address/data signal.
• Active from middle of T2 to T4.
• Tri-stated during ‘hold acknowledge’ cycle.
AD7  AD0

Signal Description of 8086

CS305 HOLD, HLDA:- Hold/Hold Acknowledge

• Hold line goes high indicates to the processor that another master
is requesting the bus access.
MODULE 1 • The processor, after receiving the HOLD request, issues the HLDA
signal in the middle of the next clock cycle after completing the
current bus cycle.
• At the same time, the processor floats the local bus and control
lines.
• When the processor deletes the HOLD line low, it lowers the
HLDA signal.
•  If a DMA request is made while the CPU is performing a memory
or I/O cycle, it will release the local bus during T4 provided.
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of the
word (or operating on an odd address).
3. The current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A lock instruction is not being executed.
AD7  AD0

Signal Description of 8086

CS305 MAXIMUM MODE: SIGNAL DESCRIPTION

S2,S1,S0 – status lines

MODULE 1 • Indicates the type of operation carried out by the processor.
• Becomes active during T4 of the previous cycle and remain active
during T1 and T2 of the current bus cycle.
• The status lines return to passive state during T3 of the current bus
cycle so that they may again become active for the next bus cycle
during T4.
• Any change in these lines during T3 indicates the starting of a new
cycle and return to passive state indicates end of the bus cycle.
AD7  AD0

Signal Description of 8086

LOCK
CS305 • indicates that other system bus masters will be prevented from
gaining the system bus, while the lock signal is low.
• Activated by the ‘lock’ prefix instruction and remains active until
MODULE 1
the completion of the next instruction.
• This floats to tri state off during hold acknowledge.
QS1, QS0- queue status
• Status of the code - prefetch queue.
• Active during the clock cycle after which the queue operation is
performed.
AD7  AD0

Signal Description of 8086

CS305 RQ/GT0, RQ/GT1- Request/grant

• Used by other local bus masters,to force the processor to release
the local bus at the end of the processors current bus cycle.
MODULE 1 • Bidirectional.
• RQ/GT0 has higher priority than RQ/GT1.

THE REQUEST/GRANT SEQUENCE IS AS FOLLOWS:

1. A pulse one clock wide from another bus master requests the bus
access to 8086.
2. During T4(current) or T1(next) clock cycle, a pulse one clock wide
from 8086 to the requesting master, indicates that the 8086 has
allowed the local bus to float and that it will enter the “hold
acknowledge” state in the next clock cycle. The CPU ’ s bus interface
unit is likely to be disconnected from the local bus of the system.
3. A one clock wide pulse from the another master indicates to 8086
that the ‘hold ’request is about to end and 8086 may regain control
of the local bus at the next clock cycle.
AD7  AD0

Signal Description of 8086

CS305

MODULE 1
AD7  AD0

Signal Description of 8086

CS305 STEPS

• The cs: ip is loaded with the required address from which the
MODULE 1 execution is to be started.
• Initially ,the queue will be empty and the microprocessor starts a
fetch operation to bring one byte of (first byte )instruction code ,if
the cs:ip address is even.
• The first byte is a complete opcode in case of some
instructions(one byte opcode )and it is a part of opcode in case of
two byte long opcode instruction,and remaining part of opcode lie
in 2nd byte.
• Opcodes along with data are fetched in the queue .when the first
byte from the queue goes for decoding, and interpretation, one byte
in the queue becomes empty and subsequently the queue is
updated.
• The microprocessor does not perform the next fetch operation till
atleast two bytes of the instruction queue are emptied.
AD7  AD0

Signal Description of 8086

CS305 • After decoding the first byte ,the decoding circuit decides whether
the instruction is of single opcode byte or double opcode byte.
• If it is single opcode byte, the next bytes in the queue are treated as
MODULE 1 data bytes. otherwise the next byte in the queue is treated as the
second byte of the instruction opcode.
• The second byte is then ,decoded in continuation with the first byte
to decide the instruction length and no of subsequent bytes to be
treated as instruction data.
• The queue is updated after every byte is read from the queue but
the fetch cycle is initiated by BIU only if atleast two bytes of the
queue are empty and EU may concurrently executing the fetched
instructions.
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