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Non-Block and Block in Verilog

This document describes the differences between non-blocking and blocking assignments in Verilog. It provides an example of a non-blocking assignment module that assigns values to registers b and c at positive clock edges from input a in a non-blocking manner. It also provides an example of a blocking assignment module that assigns values to registers b and c at positive clock edges from input a in a blocking manner. Finally, it provides an example of a module that controls an LCD display using Verilog, applying delays between sending commands and data to the LCD.

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Rohan sharma
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50 views

Non-Block and Block in Verilog

This document describes the differences between non-blocking and blocking assignments in Verilog. It provides an example of a non-blocking assignment module that assigns values to registers b and c at positive clock edges from input a in a non-blocking manner. It also provides an example of a blocking assignment module that assigns values to registers b and c at positive clock edges from input a in a blocking manner. Finally, it provides an example of a module that controls an LCD display using Verilog, applying delays between sending commands and data to the LCD.

Uploaded by

Rohan sharma
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Non-block and Block In Verilog

// Nonblocking assignments
module block_nonblock();
initial begin
reg a, b, c, d , e, f ; d <= #10 1'b1;// The simulator
assigns 1 to d at time 10
// Blocking assignments
e <= #20 1'b0;// The simulator
initial begin assigns 0 to e at time 20
a = #10 1'b1;// The simulator assigns 1 to a at time 10
f <= #40 1'b1;// The simulator
b = #20 1'b0;// The simulator assigns 0 to b at time 30 assigns 1 to f at time 40
c = #40 1'b1;// The simulator assigns 1 to c at time 70 End
end
endmodule
Blocking
module blocking (clk,a,c);
input clk; always @ (posedge
input a; clk )
output c; begin
b = a;
wire clk; c = b;
wire a;
end
reg c;
reg b;
endmodule
Non-Blocking
• module nonblocking (clk,a,c); always @ (posedge
• input clk; clk )
• input a; begin
• output c; b <= a;
• c <= b;
• wire clk; end
• wire a;
• reg c; endmodule
• reg b;
LCD Control
module lcdverilog(input clk, output data, output lcd_e, output
lcd_rw,output lcd_rs, input reset);

reg [7:0] data; // Data and command


reg [32:0] count; // counter for delay
reg [7:0] data_comand; //counter to check data and command
reg lcd_e, lcd_rw, lcd_rs; // enable, R/W and RS (i.e., command =0
or data mode=1)
LCD Control
always @(posedge clk)
begin
if(reset == 1)
begin
lcd_e=1; //enable
lcd_rw=0; //read
lcd_rs=0; // command mode
count =0;
data_comand=0;
end
LCD Control
else
begin
if (count <=1000000) ‘
begin
count = count + 1;
lcd_e = 1;
if (data_comand <=3) lcd_rs=0; else lcd_rs=1; // 4 command and 4 Data

if (data_comand==0) data = 8'b00111000; //38 i.e., 2 lines and 5×7 matrix


else if (data_comand==1) data = 8'b00001101; // 0C i.e., Display ON, cursor OFF
else if (data_comand==2) data = 8'b00000001; // 01 i.e., Clear display screen
else if (data_comand==3) data = 8'b10000010; // 82 i.e., Force cursor to beginning of first line
+2 chars
LCD Control

else if (data_comand==4) data = 8'b01000001; //A


else if (data_comand==5) data = 8'b01010010; //R
else if (data_comand==6) data = 8'b01001001; //I
else if (data_comand==7) data = 8'b01000110; //F
else data = 8'hff;
end

else if (count > 1000000 && count < 2000000) begin count = count + 1; lcd_e = 1; end // delay
else if (count >= 2000000) begin count = 0; data_comand = data_comand +1; end

if (data_comand==8) data_comand =0;


end // else-reset
end //clock end
endmodule

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