• General Info

• Purpose/
Applications

• Interrupt
Priority/ IVT Interrupts
• Controlling
Interrupts

• Maskable Nurudeen Olayiwola

interrupts
Thomas Gutierrez
• Non-maskable
interrupts

• Example

• Conclusion

1
• General Info
Question??
• Purpose/
Applications • When you are at home sitting on your lazy
• Interrupt boy, how do you know when someone
Priority/ IVT wants to talk to you on the phone?
• Controlling
Interrupts

• Maskable
interrupts – Do you periodically get up and pick up
the phone to see if someone is there?
• Non-maskable
interrupts – Or do you wait till the phone rings to
• Example
answer it?

• Conclusion

2
• General Info
Answer?
• Purpose/
Applications • The first scenario shows a person
• Interrupt
Priority/ IVT
doing what is known as polling.
• Controlling
Interrupts
• The second case illustrates an
• Maskable
interrupts interrupt-driven person.
• Non-maskable
interrupts

• Example

• Conclusion

3
• General Info
Polling
• Purpose/
Applications
• AKA “busy waiting”; looping program
• Interrupt
Priority/ IVT

• Controlling
• Continues checking status register
Interrupts until a particular state exists
• Maskable
interrupts • “Are we there yet? Are we there yet?
• Non-maskable Are we there yet?”
interrupts

• Example • What happens if something occurs at

• Conclusion other devices while the processor is
busy waiting??
4
• General Info
Interrupt
• Purpose/
Applications
• Device sends a special signal to CPU
• Interrupt when data arrives.
Priority/ IVT

• Controlling
Interrupts • “Wake me up when we get there.”
• Maskable
interrupts • Responds to hardware interrupt signal
• Non-maskable by interrupting current processing.
interrupts

• Example • Now CPU can perform tasks before

• Conclusion and after interrupt instead of just
polling!! Good!
5
• General Info
General Interrupt Flow
• Purpose/
Applications 1. Completes current instruction
2. Saves current state to status registers
• Interrupt
Priority/ IVT
3. Identify source
4. Jump to and activate Interrupt Service Routing
• Controlling (ISR)
Interrupts
5. Return to original program (RTI) and restore state
• Maskable
interrupts Register
• Non-maskable
interrupts
CPU Interrupt driven
• Example
I/O I/O
• Conclusion device device

6
• General Info
Interrupts: Flow Chart
• Purpose/
Applications
SOFTWARE HARDWARE
• Interrupt
Priority/ IVT INTERRUPT INTERRUPT

• Controlling
Interrupts STACK MPU
N MASK
REGISTER
CONTENTS SET?
• Maskable
Y
interrupts
CONTINUE MAIN
• Non-maskable SET
PROGRAM
APPROPRIATE
interrupts BIT IN CCR
$FFC0
• Example
LOAD INTERRUPT VECTOR
• Conclusion
EXECUTE INTERRUPT VECTOR INTO TABLE
SERVICE ROUTINE PROGRAM
COUNTER
$FFFF 7
• General Info
Brief Background
• Purpose/
Applications
• Univac 1103/1103A (1953-56) – first
• Interrupt
Priority/ IVT
recognized CPU with interrupts.
Current instruction was stored in
• Controlling
Interrupts memory and program counter loaded
with a fixed address.
• Maskable
interrupts

• Non-maskable • Other notables:

interrupts – IBM (1954) – first to use interrupt
• Example masking
– NBS DYSEAC (1954) – first with I/O
• Conclusion
interrupts
8
• General Info
Purpose/Applications
• Purpose/
Applications • To modify or do additional instructions based on
internal requests and/or external devices.
• Interrupt
Priority/ IVT • Provide a means for suspending current instructions
for more important tasks.
• Controlling
Interrupts
• Hardware (called Interrupts or Resets)
• Maskable – Reset
interrupts – User-defined interrupt
• Non-maskable – Timer operations
interrupts – CPU operations monitor failure

• Example • Software
– Illegal instruction
• Conclusion
– SWI

9
• General Info
Purpose/Applications (cont.)
• Purpose/
Applications • Coordinating I/O operations
• Interrupt • Notifies the CPU that an input is ready or
Priority/ IVT an output can be changed
• Controlling
Interrupts • Timing
• Maskable • Periodic (clock-driven) interrupts remind
interrupts the CPU of the passage of time
• Non-maskable • Multi-tasking
interrupts • Updating counters
• Example • Timing during interactive programs
• Errors
• Conclusion
• Interrupts can notify of error situations
10
• General Info
Purpose/Applications (cont.)
• Purpose/
Applications

• Interrupt • Practical uses/examples

Priority/ IVT
• Change direction of a motor.
• Controlling
Interrupts
• Auto wiper speed increased or
decreased.
• Maskable
interrupts • Pressing a pause button on a VCR
• Non-maskable • HC11 controlled transmission system
interrupts
• Etc.
• Example

• Conclusion

11
• General Info
Types of interrupts
• Purpose/
Applications
• Ignorable interrupts (or Maskable)
• Interrupt
Priority/ IVT – Most often used
• Controlling – Good for using when computer needs to
Interrupts do something more important
• Maskable – When the interrupt mask is set, interrupts
interrupts are hidden and therefore are ignored.
• Non-maskable • Non-ignorable interrupts (Non-
interrupts
maskable)
• Example
• NMI’s take precedence and interrupt any
• Conclusion task

12
• General Info
Interrupt Vector Table
• Purpose/
Applications
• When an interrupt occurs, control of the
• Interrupt
Priority/ IVT
program moves to the interrupt handling
routine
• Controlling
– Event similar to subroutine
Interrupts
– How do we know where the handler routine is
• Maskable though??
interrupts
• The address of the handler is provided by
• Non-maskable the interrupt vector table
interrupts
– IVT has one entry for each type of interrupt
• Example – Each entry is indexed by interrupt type, and
includes a pointer to the handler
• Conclusion

13
 Maskable when the I-
Interrupt Vector Table bit of CCR is set

• General Info

• Purpose/
Applications lowest priority

• Interrupt
Priority/ IVT

• Controlling
Interrupts

• Maskable
interrupts

• Non-maskable
interrupts

• Example highest priority

• Conclusion

14
Unmaskable
• General Info
Maskable/Unmaskable
• Purpose/
Applications
• 6 Non-Maskable
• Interrupt
Priority/ IVT – always interrupt the program
• Controlling execution
Interrupts
• 15 Maskable
• Maskable
interrupts – can enable or disable by mask bits
• Non-maskable – HOW?
interrupts

• Example

• Conclusion

15
• General Info
Stacking order
• Purpose/ When an interrupt occurs:
SP-9
Applications 1. Finish execution of the current instruction SP-8 CCR
Note: Non-maskable interrupts and resets SP-7 ACCB
• Interrupt happen immediately
SP-6 ACCA
Priority/ IVT
2. HC11 pushes on stack: SP-5 IXH
• Controlling PC, accumulators and registers, CCR SP-4 IXL
Interrupts SP-3 IYH
3. HC11 sets the I-bit
SP-2 IYL
• Maskable Masks interrupts - can’t interrupt an interrupt
SP-1 PCH
interrupts 4. Looks up vector of highest-priority interrupt
SP-0 PCL
• Non-maskable 5. Branches to interrupt service routine
interrupts Executes until RTI is encountered

• Example 6. Restores accumulators and registers, CCR from stack

(note: this includes restoring the I-bit of CCR)
• Conclusion
7. Returns to instruction after the one that was interrupted
(note: other interrupts may be pending now)
16
• General Info
Controlling Interrupts: The I-bit
• Purpose/
Applications • Exists as bit 4 in the Condition Code
• Interrupt Register (CCR)
Priority/ IVT
– When set (I=1), interrupts will be inhibited and
• Controlling placed as pending
Interrupts – When cleared (I=0), interrupt servicing will be
• Maskable
allowed when asked
interrupts • The I bit is always set while servicing
• Non-maskable an interrupt; Interrupts can’t nest
interrupts
• Set during RESET to allow minimum
• Example
system initialization
• Conclusion

17
• General Info
Controlling Interrupts: The I-bit
• Purpose/
Applications • Can also be set by software to
• Interrupt prevent execution of maskable
Priority/ IVT
interrupts
• Controlling
– SEI (SEt Interrupt Mask)
Interrupts

• Maskable
• Can be cleared by software
interrupts instructions
• Non-maskable – CLI (CLear Interrupt Mask)
interrupts
• Automatically cleared by RTI
• Example
instruction
• Conclusion

18
• General Info
Maskable Interrupt: HPRIO
• Purpose/
Applications

• Interrupt
• Can elevate the priority of one of
Priority/ IVT the maskable interrupts.
• Controlling
Interrupts • Uses bits 0-3 of HPRIO (Highest
• Maskable PRIOrity Interrupt Register)
interrupts
• Default is IRQ.
• Non-maskable
interrupts • Can be set at anytime during
• Example program as long as I bit is set.
• Conclusion

19
• General Info
Maskable Interrupt: IRQ
• Purpose/
Applications
• Highest priority maskable interrupt
• Interrupt • IRQ pin provides additional external
Priority/ IVT interrupting source
• Controlling • Other additional MCU pins can be used as
Interrupts interrupt inputs:
– Example:
• Maskable • XIRQ input
interrupts • Main-Timer Capture Pins
• Pulse Accumulator Pin
• Non-maskable
interrupts • IRQE Bit in the OPTION control used to
specify IRQ pin configuration
• Example – IRQE = 0 -> Low level sensitive
– IRQE = 1 -> Low-going edge sensitive (single
• Conclusion
source only)

20
• General Info
Maskable Interrupt: IRQ
• Purpose/
Applications

• Interrupt
• Controlled by a pin on the HC11
Priority/ IVT
• A low signal will initiate interrupt
• Controlling
Interrupts sequence
• Maskable OPTION $1039
interrupts 7 6 5 4 3 2 1 0
• Non-maskable ADPU CSEL IRQE DLY CME CR1 CR0
interrupts
IRQE = IRQ Select Edge Sensitive Only (Time Protected)
• Example
0 0 = IRQ configured for low LEVEL (default)
• Conclusion 1 1 = IRQ configured for falling EDGEs

21
• General Info
Non-maskable Interrupt: XIRQ
• Purpose/
Applications
• Enabled by TAP instruction by clearing X-bit
• Interrupt upon system initialization
Priority/ IVT
• After being cleared, software cannot set the
• Controlling X-bit, thus XIRQ is non-maskable.
Interrupts
• Higher priority than any source maskable by
• Maskable the I-bit.
interrupts
• Both the X and I bits are automatically set
• Non-maskable by hardware after stacking the CCR.
interrupts • RTI restores X and I bit to pre-interrupt
• Example states
• Conclusion

22
• General Info
Non-maskable Interrupt: SWI
• Purpose/
Applications
• Software instruction, thus cannot be
• Interrupt
Priority/ IVT interrupted until completed
• Controlling • Uninhibited by global mask bits in the
Interrupts
CCR
• Maskable
interrupts
• Similar to other interrupts, sets the I-
• Non-maskable
bit upon servicing
interrupts

• Example

• Conclusion

23
• General Info
Example - IRQ handler
>>Whenever button is pushed,
update a counter and print out
• Purpose/ 1. Write the IRQ handler routine
IRQHANDLE ORG $3000
the current count
Applications
ldaa count ; A <-- current count
inca ; increment count
• Interrupt staa count ; write back count
Priority/ IVT ldx #msg ; print out msg
jsr OUTSTRG
ldx #count ; print out count
• Controlling jsr OUT1BYT
Interrupts rti ; all done – return
org $2000 ; data section
• Maskable 2. Write the initialization and main routine
interrupts
msg fcc “Number of times button pressed:”
fcb $04
• Non-maskable
interrupts count fcb 0 ; button counter
org $00ee
JMP IRQHANDLE IRQ vector
• Example at $FFF2

3. Do-nothing program!
• Conclusion
org $2200 ; main program
cli ; enable interrupts
loop bra loop ; endless loop 24
• General Info
The SIX untouchables: NONMASKABLE
• Purpose/
Applications

• Interrupt
• RESET
Priority/ IVT
• CLOCK MONITOR
• Controlling
Interrupts • COP Watchdog
• Maskable
interrupts
• Illegal Opcode
• Non-maskable • XIRQ
interrupts
• SWI
• Example

• Conclusion

25
• General Info
Advantages and Disadvantages
• Purpose/
Applications

• Interrupt
• Advantage
Priority/ IVT
1. Efficient, better than polling
• Controlling
Interrupts 2. Multitasking
• Maskable
interrupts

• Non-maskable
• Disadvantage
interrupts
1. They can occur randomly
• Example
2. Requires additional hardware,
• Conclusion
sometimes
26
• General Info

• Purpose/
Applications

• Interrupt
Priority/ IVT

• Controlling
Interrupts
Questions??
• Maskable
interrupts

• Non-maskable
interrupts

• Example

• Conclusion

27
• General Info
References
• Purpose/
Applications
http://courses.cs.tamu.edu/cpsc462/
• Interrupt walker/Slides/Exceptions_Interrupts_1.ppt
Priority/ IVT
http://oa-003.spu.edu/bolding/ee3280/nosound/16-Exceptions.
• Controlling ppt
Interrupts

• Maskable Previous semester presentations…

interrupts

• Non-maskable
interrupts

• Example

• Conclusion

28