KEC-502

MICROPROCESSOR
&
MICROCONTROLLER

By:
Rajni Parashar
Asst. Prof. ECE
 UNIT II

• Basic Programming concepts:, Flow chart

symbols, Data Transfer operations, Arithmetic
operations, Logic Operations, Branch operation,

• Writing assembly language programs,

Programming techniques: looping, counting and
indexing. Additional data transfer and 16 bit
arithmetic instruction, Logic operation: rotate,
compare, counter and time delays, 8085
Interrupts.
 TEXT BOOKS
• Ramesh Gaonkar, “Microprocessor Architecture,
Programming, and Applications with the 8085”, 5 th
Edition, Penram International Publication (India) Pvt.
Ltd.,2009
 Operand Types

• There are different ways for specifying the

operand:
– There may not be an operand (implied
operand)
• CMA
– The operand may be an 8-bit number
(immediate data)
• ADI 4FH
– The operand may be an internal register
(register)
• SUB B
– The operand may be a 16-bit address (memory
address)
 Instruction Size

• Depending on the operand type, the instruction

may have different sizes. It will occupy a different
number of memory bytes.
– Typically, all instructions occupy one byte only.
– The exception is any instruction that contains
immediate data or a memory address.
• Instructions that include immediate data use two
bytes.
– One for the opcode and the other for the 8-bit data.
• Instructions that include a memory address
occupy three bytes.
– One for the opcode, and the other two for the 16-
bit address.
 Instruction with Immediate Date

• Operation: Load an 8-bit number into the

accumulator.

– MVI A, 32
• Operation: MVI A
• Operand: The number 32
• Binary Code:
0011 1110 3E 1st byte.
0011 0010 32 2nd
byte.
 Instruction with a Memory
Address
• Operation: go to address 2085.

– Instruction: JMP 2085

• Opcode: JMP
• Operand: 2085
• Binary code:
1100 0011 C3 1st
byte.
1000 0101 85 2nd byte
0010 0000 20 3rd byte
 Addressing Modes

• The microprocessor has different ways of

specifying the data for the instruction. These are
called “addressing modes”.

• The 8085 has four addressing modes:

– Implied CMA
– Immediate MVI B, 45
– Direct LDA 4000
– Indirect LDAX B
• Load the accumulator with the contents of the memory location
whose address is stored in the register pair BC).
 ADDRESSING MODES
1. Immediate: 8 or 16 bit data is a part of instruction. Eg MVI R,
data, LXI Rp, Data

2. Register: Both source and destination operands are specified by

8085 Registers. Eg. MOV B,C

3. Direct: 16 bit memory address is directly specified within the

instruction. Eg: LDA address.

4. Indirect: memory address is specified with the help of register pair.

Eg: LDAX Rp

5. Implied: Opcode specifies the operand. eg: CMA

 Data Formats

• In an 8-bit microprocessor, data can be

represented in one of four formats:
• ASCII
• BCD
• Signed Integer
• Unsigned Integer.

– It is important to recognize that the microprocessor

deals with 0’s and 1’s.
• It deals with values as strings of bits.
• It is the job of the user to add a meaning to these strings.
 Data Formats

• Assume the accumulator contains the following

value: 0100 0001.
– There are four ways of reading this value:
• It is an unsigned integer expressed in binary, the equivalent
decimal number would be 65.
• It is a number expressed in BCD (Binary Coded Decimal)
format. That would make it, 41.
• It is an ASCII representation of a letter. That would make it the
letter A.
• It is a string of 0’s and 1’s where the 0th and the 6th bits are set
to 1 while all other bits are set to 0.

ASCII stands for American Standard Code for Information Interchange.

 The 8085 Instructions

– Since the 8085 is an 8-bit device it can have up to 28

(256) instructions.
• However, the 8085 only uses 246 combinations that represent a
total of 74 instructions.
– Most of the instructions have more than one format.

– These instructions can be grouped into five different

groups:
• Data Transfer Operations
• Arithmetic Operations
• Logic Operations
• Branch Operations
• Machine Control Operations
 Instruction and Data Formats

• Each instruction has two parts.

– The first part is the task or operation to be
performed.
• This part is called the “opcode” (operation
code).

– The second part is the data to be operated

on
• Called the “operand”.
 Data Transfer Operations

– These operations simply COPY the data from the

source to the destination.
– MOV, MVI, LDA, and STA

– They transfer:
• Data between registers.
• Data Byte to a register or memory location.
• Data between a memory location and a register.
• Data between an I\O Device and the accumulator.

– The data in the source is not changed.

 Opcode Operand Description
1. Copy from source to destination
MOV Rd, Rs This instruction copies the contents of the
M, Rs
Rd, M source register into the destination register; the
contents of the source register are not altered. If
one of the operands is a memory location, its
location is specified by the contents of the HL
registers.
Example: MOV B, C or MOV B, M
2. Move immediate 8-bit

MVI Rd, data The 8-bit data is stored in the destination

M, data
register or memory. If the operand is a memory
location, its location is specified by the
contents of the HL registers.
Example: MVI B, 57 or MVI M, 57
3. Load register pair immediate
LXI Reg. pair, 16-bit data The instruction loads 16-bit data in the register pair
designated in the operand.
Example: LXI H, 2034

4. Load accumulator
LDA 16-bit The contents of a memory location, specified
address
by a16-bit address in the operand, are copied
to the accumulator. The contents of the source
are not altered.
Example: LDA 2034 or LDA XYZ
 5.Store accumulator direct
STA 16-bit The contents of the accumulator are copied
address
into the memory location specified by the
operand. This is a 3-byte instruction, the
second byte specifies the low-order address
and the third byte specifies the high-order
address.
Example: STA 4350 or STA XYZ
6.Load accumulator indirect
LDAX B/D Reg. The contents of the designated register pair
pair
point to a memory location. This instruction
copies the contents of that memory location
into the accumulator. The contents of either
the register pair or the memory location are
not altered.
Example: LDAX B
7. Store accumulator indirect
STAX Reg. pair The contents of the accumulator are copied
into the memory location specified by the
contents of the operand (register pair). The
contents of the accumulator are not altered.
Example: STAX B
8. Load H and L registers direct

LHLD 16-bit The instruction copies the contents of the memory location
address pointed out by the 16-bit address into register L and copies
the contents of the next memory location into register H.
The contents of source memory locations are not altered.
Example: LHLD 2040
9. Store H and L register Direct
SHLD 16-bit address The contents of register L are stored into the memory
location specified by the 16-bit address in the operand and
the contents of H register are stored into the next memory
location by incrementing the operand. The contents of
registers HL are not altered. This is a 3-byte instruction,
the second byte specifies the low-order address and the
third byte specifies the high-order address.
Example: SHLD 2470
10. Exchange H and L with D and E
XCHG none
The contents of register H are exchanged with the contents
of register D, and the contents of register L are exchanged
with the contents of register E.
Example: XCHG
 The LXI instruction
• The 8085 provides an instruction to place
the 16-bit data into the register pair in one
step.
• LXI Rp, <16-bit address> (Load
eXtended Immediate)

– The instruction LXI B 4000H will place the

16-bit number 4000 into the register pair B, C.
• The upper two digits are placed in the 1st register of
the pair and the lower two digits in the 2nd .

LXI B 40 00H B 40 00 C
 The Memory “Register”

• Most of the instructions of the 8085 can use a

memory location in place of a register.
– The memory location will become the “memory” register
M.
• MOV M B
– copy the data from register B into a memory location.
– Which memory location?

• The memory location is identified by the contents

of the HL register pair.
– The 16-bit contents of the HL register pair are treated
as a 16-bit address and used to identify the memory
location.
 Using the Other Register
Pairs
– There is also an instruction for moving data from
memory to the accumulator without disturbing the
contents of the H and L register.

• LDAX Rp (LoaD Accumulator eXtended)

– Copy the 8-bit contents of the memory location identified by the

Rp register pair into the Accumulator.
– This instruction only uses the BC or DE pair.
– It does not accept the HL pair.
 Indirect Addressing Mode

• Using data in memory directly (without loading

first into a Microprocessor’s register) is called
Indirect Addressing.

• Indirect addressing uses the data in a register pair

as a 16-bit address to identify the memory location
being accessed.
– The HL register pair is always used in conjunction with
the memory register “M”.
– The BC and DE register pairs can be used to load data
into the Accumultor using indirect addressing.
 Arithmetic Operations

– Addition (ADD, ADI):

– Any 8-bit number.
– The contents of a register.
– The contents of a memory location.
• Can be added to the contents of the accumulator and the result
is stored in the accumulator.

– Subtraction (SUB, SUI):

– Any 8-bit number
– The contents of a register
– The contents of a memory location
• Can be subtracted from the contents of the accumulator. The
result is stored in the accumulator.
Arithmetic Operations Related
to Memory
• These instructions perform an arithmetic operation
using the contents of a memory location while
they are still in memory.
– ADD M
• Add the contents of M to the Accumulator
– SUB M
• Sub the contents of M from the Accumulator
– INR M / DCR M
• Increment/decrement the contents of the memory location in
place.

– All of these use the contents of the HL register pair to

identify the memory location being used.
 Arithmetic Operations

– Increment (INR) and Decrement (DCR):

• The 8-bit contents of any memory location or any
register can be directly incremented or decremented
by 1.
• No need to disturb the contents of the accumulator.
Opcode Operand Description
Add register or memory to accumulator
ADD R
M The contents of the operand (register or memory) are added to
the contents of the accumulator and the result is stored in the
accumulator. If the operand is a memory location, its location
is specified by the contents of the HLregisters. All flags are
modified to reflect the result of the addition.
Example: ADD B or ADD M
Add register to accumulator with carry
ADC R The contents of the operand (register or memory) and the Carry
M
flag are added to the contents of the accumulator and the result
is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the
addition.
Example: ADC B or ADC M
Add immediate to accumulator
ADI 8-bit data The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator. All
flags are modified to reflect the result of the addition.
Example: ADI 45
Add immediate to accumulator with carry
ACI 8-bit data The 8-bit data (operand) and the Carry flag are added to
the contents of the accumulator and the result is stored
in the accumulator. All flags are modified to reflect the
result of the addition.
Example: ACI 45
Add register pair to H and L registers
DAD Reg. pair The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is
stored in the HL register. The contents of the source
register pair are not altered. If the result is larger than 16
bits, the CY flag is set. No other flags are affected.
Example: DAD H

SUB R The contents of the operand (register or memory ) are

M
subtracted from the contents of the accumulator, and the
result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents
of the HL registers. All flags are modified to reflect the
result of the subtraction.
Example: SUB B or SUB M
Subtract source and borrow from accumulator
SBB R The contents of the operand (register or memory ) and the
Borrow flag are subtracted from the contents of the
accumulator and the result is placed in the accumulator. If
the operand is a memory location, its location is specified by
the contents of the HL registers. All flags are modified to
reflect the result in accumulator.
Example: SBB B or SBB M

Subtract immediate from accumulator

SUI 8 BIT DATA The 8-bit data (operand) is subtracted from the contents of the
accumulator and the result is stored in the accumulator. All
flags are modified to reflect the result of the subtraction.
Example: SUI 45

Subtract immediate from accumulator with borrow

SBI 8 BIT DATA The 8-bit data (operand) and the Borrow flag are subtracted
from the contents of the accumulator and the result is stored
in the accumulator. All flags are modified to reflect the result
of the subtraction.
Example: SBI 45
Increment register or memory by 1
INR R The contents of the designated register or memory) are incremented by 1
M and the result is stored in the same place. If the operand is a memory
location, its location is specified by the contents of the HL registers.
Example: INR B or INR M
Increment register pair by 1
INX Rp The contents of the designated register pair are incremented by 1 and the
result is stored in the same place.
Example: INX H
Decrement register or memory by 1
DCR R The contents of the designated register or memory are decremented by 1
M and the result is stored in the same place. If the operand is a memory
location, its location is specified by the contents of the HL registers.
Example: DCR B or DCR M
Decrement register pair by 1
DCX Rp The contents of the designated register pair are decremented by 1 and the
result is stored in the same place.
Example: DCX H
 DAA: Decimal Adjust Accumulator/ Decimal Adjust after addition

 The contents of the accumulator are changed from a binary value to two 4-
bit binary coded decimal (BCD) digits. This is the only instruction that uses
the auxiliary flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY flags are altered to
reflect the results of the operation.
  
 If the value of the low-order 4-bits in the accumulator is greater than 9 or if
AC flag is set, the instruction adds 6 to the low-order four bits.
  
 If the value of the high-order 4-bits in the accumulator is greater than 9 or
if the Carry flag is set, the instruction adds 6 to the high-order four bits.
  
 Example: DAA
 Manipulating Addresses

 Now that we have a 16-bit address in a register pair, how

do we manipulate it?
– It is possible to manipulate a 16-bit
address stored in a register pair as one
entity using some special instructions.
• INX Rp (Increment the 16-bit number in the register pair)
• DCX Rp (Decrement the 16-bit number in the register pair)

– The register pair is incremented or decremented as one

entity. No need to worry about a carry from the lower
8-bits to the upper. It is taken care of automatically.
 Logic Operations
• These instructions perform logic operations on the
contents of the accumulator.
– ANA, ANI, ORA, ORI, XRA and XRI
• Source: Accumulator and
– An 8-bit number
– The contents of a register
– The contents of a memory location
• Destination: Accumulator
ANA R/M AND Accumulator With Reg/Mem
ANI # AND Accumulator With an 8-bit number

ORA R/M OR Accumulator With Reg/Mem

ORI # OR Accumulator With an 8-bit number

XRA R/M XOR Accumulator With Reg/Mem

XRI # XOR Accumulator With an 8-bit number
 Logic Operations

– Complement:
• 1’s complement of the contents of the accumulator.
CMA No operand

– STC: SET CARRY FLAG

– CMC: COMPLEMENT CARRY FLAG
 Additional Logic Operations

• Rotate
– Rotate the contents of the accumulator one
position to the left or right.
– RLC Rotate the accumulator left.
Bit 7 goes to bit 0 AND the Carry flag.
– RAL Rotate the accumulator left through the carry.
Bit 7 goes to the carry and carry goes to bit
– RRC 0.
Rotate the accumulator right.
– RAR Bit 0 goes to bit 7 AND the Carry flag.
Rotate the accumulator right through the carry.
Bit 0 goes to the carry and carry goes to bit 7.
 RLC vs. RLA
Carry Flag

• RLC
7 6 5 4 3 2 1 0

Accumulator

Carry Flag

• RAL 7 6 5 4 3 2 1 0

Accumulator
 Logical Operations

• Compare
• Compare the contents of a register or memory location with the
contents of the accumulator.
– CMP R/M Compare the contents of the register
or memory location to the contents of
the accumulator.
– CPI # Compare the 8-bit number to the
contents of the accumulator.
• The compare instruction sets the flags (Z, Cy, and S).

• The compare is done using an internal subtraction that does not

change the contents of the accumulator.
A – (R / M / #)
 STACK INSTRUCTIONS
 Copy H and L registers to the stack pointer
SPHL The instruction loads the contents of the H and L registers into the stack
pointer register, the contents of the H register provide the high-order address
and the contents of the L register provide the low-order address. The contents
of the H and L registers are not altered.
Example: SPHL
Exchange H and L with top of stack
XTHL The contents of the L register are exchanged with the stack location pointed
out by the contents of the stack pointer register. The contents of the H
register are exchanged with the next stack location (SP+1); however, the
contents of the stack pointer register are not altered.
Example: XTHL
Push register pair onto stack
PUSH Rp  The contents of the register pair designated in the operand are copied onto
the stack in the following sequence. The stack pointer register is decremented
and the contents of the high-order register (B, D, H, A) are copied into that
location. The stack pointer register is decremented again and the contents of
the low- order register (C, E, L, flags) are copied to that location.
Example: PUSH B or PUSH A
Pop off stack to register pair
POP Rp The contents of the memory location pointed out by the stack pointer
register are copied to the low-order register (C, E, L, status flags) of
the operand. The stack pointer is incremented by 1 and the contents
of that memory location are copied to the high-order register (B, D,
H, A) of the operand. The stack pointer register is again incremented
by 1.
Example: POP H or POP A
PUSH PSW  The stack pointer register is decremented and the contents of A are
copied into that location. The stack pointer register is decremented
again and the contents of flag register are copied to that location.
POP PSW The contents of the memory location pointed out by the stack pointer
register are copied to the status flags. The stack pointer is
incremented by 1 and the contents of that memory location are
copied to the high-order register A of the operand. The stack pointer
register is again incremented by 1.
 Branch Operations

• Two types:
– Unconditional branch.
• Go to a new location no matter what.
– Conditional branch.
• Go to a new location if the condition is true.
 Unconditional Branch

– JMP Address
• Jump to the address specified (Go to).

– CALL Address
• Jump to the address specified but treat it as a subroutine.

– RET
• Return from a subroutine.

– The addresses supplied to all branch operations must be

16-bits.
 Conditional Branch

– Go to new location if a specified condition is met.

• JZ Address (Jump on Zero)
– Go to address specified if the Zero flag is set.
• JNZ Address (Jump on NOT Zero)
– Go to address specified if the Zero flag is not set.
• JC Address (Jump on Carry)
– Go to the address specified if the Carry flag is set.
• JNC Address (Jump on No Carry)
– Go to the address specified if the Carry flag is not set.
• JP Address (Jump on Plus)
– Go to the address specified if the Sign flag is not set
• JM Address (Jump on Minus)
– Go to the address specified if the Sign flag is set.
CALL conditionally:
The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand based on the
specified flag of the PSW as described below. Before the transfer,
the address of the next instruction after the call (the contents of
the program counter) is pushed onto the stack.

 Opcode Description Flag Status

 CC Call on Carry CY = 1
 CNC Call on no Carry CY = 0
 CP Call on positive S=0
 CM Call on minus S=1
 CZ Call on zero Z=1
 CNZ Call on no zero Z=0
 CPE Call on parity even P=1
 CPO Call on parity odd P=0
CONDITIONAL RETURN

The program sequence is transferred from the subroutine to the

calling program based on the specified flag of the PSW as described
below. The two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new address.

 Opcode Description Flag Status

 RC Return on Carry CY = 1
 RNC Return on no Carry CY = 0
 RP Return on positive S=0
 RM Return on minus S=1
 RZ Return on zero Z=1
 RNZ Return on no zero Z=0
 RPE Return on parity even P = 1
 RPO Return on parity odd P = 0
 Machine Control

– HLT
• Stop executing the program.
– NOP
• No operation
• Exactly as it says, do nothing.
• Usually used for delay or to replace instructions
during debugging.
Disable interrupts
DI none The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No
flags are affected. Example: DI
Enable interrupts
EI none The interrupt enable flip-flop is set and all
interrupts are enabled. No flags are affected.
After a system reset or the acknowledgement of
an interrupt, the interrupt enable flip-flop is
reset, thus disabling the interrupts. This
instruction is necessary to reenable the interrupts
(except TRAP). Example: EI
SIM: Set interrupt mask 
RIM:READ INTERRUPT MASK
This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and
read serial data input bit. The instruction loads eight bits in the accumulator with
the following interpretations
 INPUT/OUTPUT INSTRUCTIONS

 OUT 8-bit port address

 The contents of the accumulator are copied into the I/O port
specified by the operand.
 Example: OUT 87

 IN 8-bit port address

 The contents of the input port designated in the operand are read
and loaded into the accumulator.
 Example: IN 82
Counters & Time Delays
 Counters

• A loop counter is set up by loading a register with

a certain value
• Then using the DCR (to decrement) and INR (to
increment) the contents of the register are updated.
• A loop is set up with a conditional jump
instruction that loops back or not depending on
whether the count has reached the termination
count.
 Counters
• The operation of a loop counter can be
described using the following flowchart.

Initialize

Body of loop

Update the count

No Is this
Final
Count?

Ye
s
Sample ALP for implementing a
loop Using DCR instruction
MVI C, 15H
LOOP DCR C
JNZ LOOP
 Using a Register Pair as a
Loop Counter
 Using a single register, one can repeat a loop for a
maximum count of 255 times.

 It is possible to increase this count by using a register

pair for the loop counter instead of the single register.
 A minor problem arises in how to test for the
final count since DCX and INX do not
modify the flags.
 However, if the loop is looking for when the
count becomes zero, we can use a small trick
by ORing the two registers in the pair and
then checking the zero flag.
Using a Register Pair as a
Loop Counter
• The following is an example of a loop set
up with a register pair as the loop counter.

LXI B, 1000H
LOOP DCX B
MO
V A, C
ORA B
JNZ LOOP
 Delays

• It was shown in Chapter 2 that each instruction

passes through different combinations of Fetch,
Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can
calculate how long such an instruction
would require to complete.
• The table in Appendix F of the book contains a
column with the title B/M/T.
– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State.
 Delays

• Knowing how many T-States an instruction

requires, and keeping in mind that a T-State is one
clock cycle long, we can calculate the time using
the following formula:

Delay = No. of T-States / Frequency

• For example a “MVI” instruction uses 7 T-States.

Therefore, if the Microprocessor is running at 2
MHz, the instruction would require 3.5 Seconds
to complete.
 Delay loops
• We can use a loop to produce a certain
amount of time delay in a program.

• The following is an example of a delay

loop:
MVI C, FFH 7 T-States
LOOP DCR C 4 T-States
JNZ 10 T-States
LOOP
• The first instruction initializes the loop counter and is
executed only once requiring only 7 T-States.
• The following two instructions form a loop that
requires 14 T-States to execute and is repeated 255
times until C becomes 0.
 Delay Loops (Contd.)

• We need to keep in mind though that in the last

iteration of the loop, the JNZ instruction will fail and
require only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total
delay to get an accurate delay calculation.
• To calculate the delay, we use the following
formula:
Tdelay = TO + TL
– Tdelay = total delay
– TO = delay outside the loop
– TL = delay of the loop
 Delay Loops (Contd.)

• Using these formulas, we can calculate the

time delay for the previous example:

• TO = 7 T-States
– Delay of the MVI instruction

• TL = (14 X 255) - 3 = 3567 T-States

– 14 T-States for the 2 instructions repeated 255 times
(FF16 = 25510) reduced by the 3 T-States for the final
JNZ.
 Using a Register Pair as a
Loop Counter
 Using a single register, one can repeat a loop for a
maximum count of 255 times.

 It is possible to increase this count by using a register

pair for the loop counter instead of the single register.
 A minor problem arises in how to test for the
final count since DCX and INX do not
modify the flags.
 However, if the loop is looking for when the
count becomes zero, we can use a small trick
by ORing the two registers in the pair and
then checking the zero flag.
Using a Register Pair as a
Loop Counter
• The following is an example of a delay loop
set up with a register pair as the loop
counter.

LXI B, 1000H 10 T-States

LOOP DCX B 6 T-States
MO 4 T-States
V A, C 4 T-States
ORA B 10 T-States
JNZ LOOP
Using a Register Pair as a
Loop Counter
• Using the same formula from before, we can
calculate:

• TO = 10 T-States
– The delay for the LXI instruction

• TL = (24 X 4096) - 3 = 98301 T- States

– 24 T-States for the 4 instructions in the loop repeated
4096 times (100016 = 409610) reduced by the 3 T-
States for the JNZ in the last iteration.
 Nested Loops Initialize loop 2

Body of loop 2

• Nested loops can be Initialize loop 1

easily setup in Body of loop 1

Assembly language by Update the count1

using two registers

Is this
for the two loop No
Final
Count?
counters and updating Ye
the right register in Update the scount 2

the right loop. Is this

No
– In the figure, the body of Final
Count?
loop2 can be before or
Ye
after loop1. s
 Nested Loops for Delay

• Instead (or in conjunction with) Register Pairs, a

nested loop structure can be used to increase
the total delay produced.

MVI B, 10H 7 T-States

LOOP2 MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States
 Delay Calculation of Nested
Loops
• The calculation remains the same except
that it the formula must be applied
recursively to each loop.
– Start with the inner loop, then plug that delay in
the calculation of the outer loop.

• Delay of inner loop

– TO1 = 7 T-States
• MVI C, FFH instruction
– TL1 = (255 X 14) - 3 = 3567 T-States
• 14 T-States for the DCR C and JNZ instructions repeated 255
 Delay Calculation of Nested
Loops
• Delay of outer loop
– TO2 = 7 T-States
• MVI B, 10H instruction
– TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
• 14 T-States for the DCR B and JNZ instructions and 3574
T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the
final JNZ.
– TDelay = 7 + 57405 = 57412 T-States

• Total Delay
– TDelay = 57412 X 0.5 Sec = 28.706 mSec
 Increasing the delay

• The delay can be further increased by using

register pairs for each of the loop counters
in the nested loops setup.
• It can also be increased by adding dummy
instructions (like NOP) in the body of the
loop.
 Timing Diagram
Instruction:
A000h MOV
A,B

Corresponding Coding:
A000h 78
 Timing Diagram
Instruction:
A000h MOV
A,B
Corresponding Coding:
A000h 78

OFC

8085 Memory
 Timing Diagram
Instruction: T1 T2 T3 T4

A000h MOV A0h

A15- A8 (Higher Order Address
A,B bus)

Corresponding Coding: 00h 78h

A000h 78
ALE

RD

OFC WR

IO/M
8085 Memory
Op-code fetch Cycle
 Timing Diagram
Instruction:
A000h MVI
A,45h
Corresponding Coding:
A000h 3E
45
A001h
 Timing Diagram
Instruction:
A000h MVI
A,45h
Corresponding Coding: OFC
A000h 3E
MEMR

45
A001h 8085 Memory
 Timing Diagram
T1 T2 T3 T4 T5 T6 T7

A0h A0h
A15- A8 (Higher Order Address bus)
00h 3Eh 01h 45h
DA7-DA0 (Lower order address/data Bus)
Instruction:
A000h MVI A,45h
ALE
Corresponding Coding:
RD
A000h 3E
45
WR
A001h

IO/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram
Instruction:
A000h LXI
A,FO45h
Corresponding Coding:
A000h 21
45
A001h F0

A002h
 Timing
Diagram

Instruction:
A000h LXI
A,FO45h
OFC
Corresponding Coding:
A000h 21 MEMR

MEMR
45
A001h F0 8085 Memory

A002h
 Timing Diagram

Op-Code Fetch Cycle Memory Read Cycle Memory Read Cycle

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

A0h A0h A0h

A15- A8 (Higher Order Address bus)
00h 21h 01h 45h 02h F0h
DA7-DA0 (Lower order address/data Bus)

ALE

RD

WR

IO/M
 Timing Diagram
Instruction:
A000h MOV
A,M
Corresponding Coding:
A000h 7E
 Timing Diagram

Instruction:
A000h MOV
OFC
A,M
MEMR
Corresponding Coding:
A000h 7E 8085 Memory
 Timing Diagram

T1 T2 T3 T4 T5 T6
A0h T7
A15- A8 (Higher Order Address bus) Content Of Reg H
00h 7Eh L Reg Content Of M
Instruction: DA7-DA0 (Lower order address/data Bus)

A000h MOV A,M

Corresponding Coding: ALE
A000h 7E
RD

WR

IO/M

Op-Code Fetch Cycle Memory Read Cycle

 Timing Diagram

Instruction:
A000h MOV M,A
Corresponding Coding:
A000h 77
 Timing Diagram

Instruction:
A000h MOV M,A
OFC
Corresponding Coding: MEMW

A000h 77
8085 Memory
 Timing Diagram

T1 T2 T3 T4 T5 T6
A0h T7
A15- A8 (Higher Order Address bus) Content Of Reg H
00h 7Eh L Reg Content of Reg A
Instruction: DA7-DA0 (Lower order address/data Bus)

A000h MOV M,A

Corresponding Coding: ALE
A000h 77
RD

WR

IO/M

Op-Code Fetch Cycle Memory Write Cycle

 The Stack

• The stack is an area of memory identified by the

programmer for temporary storage of information.
• The stack is a LIFO structure.
– Last In First Out.
• The stack normally grows backwards into Memory

memory.
– In other words, the programmer
defines the bottom of the stack The Stack
and the stack grows up into grows
backwards
reducing address range. into memory
Bottom
of the
Stack
 The Stack

• Given that the stack grows backwards into

memory, it is customary to place the bottom of the
stack at the end of memory to keep it as far away
from user programs as possible.
• In the 8085, the stack is defined by setting the SP
(Stack Pointer) register.

LXI SP, FFFFH

• This sets the Stack Pointer to location FFFFH (end

of memory for the 8085).
 Saving Information on the Stack

• Information is saved on the stack by PUSHing it

on.
– It is retrieved from the stack by POPing it off.

• The 8085 provides two instructions: PUSH and

POP for storing information on the stack and
retrieving it back.
– Both PUSH and POP work with register pairs
ONLY.
 The PUSH Instruction

• PUSH B
– Decrement SP
– Copy the contents of register B to the memory
location pointed to by SP
– Decrement SP C
B
12 F 3 ister C to the
– Copy the co nten t s of reg
FFFB

memory
location pointed to by SP
FFFC
FFFD
F3
FFFE 12 SP
FFFF
 The POP Instruction

• POP D
– Copy the contents of the memory location
pointed to by the SP to register E
– Increment SP
– Copy the contents
D E
of the memory location
pointed to by
12 the
F3 P to regist er D
– IncrementS SP
FFFB

FFFC SP
F3
FFFD 12
FFFE

FFFF
 Operation of the Stack

• During pushing, the stack operates in a

“decrement then store” style.
– The stack pointer is decremented first, then the
information is placed on the stack.

• During poping, the stack operates in a “use then

increment” style.
– The information is retrieved from the top of the the
stack and then the pointer is incremented.

• The SP pointer always points to “the top of the

 LIFO

• The order of PUSHs and POPs must be opposite

of each other in order to retrieve information back
into its original location.

PUSH B
PUSH
D
...
POP D
POP
B
 The PSW Register Pair

• The 8085 recognizes one additional register pair

called the PSW (Program Status Word).
– This register pair is made up of the Accumulator and
the Flags registers.

• It is possible to push the PSW onto the stack, do

whatever operations are needed, then POP it off of
the stack.
– The result is that the contents of the Accumulator and
the status of the Flags are returned to what they were
before the operations were executed.
 Subroutines

• A subroutine is a group of instructions that will be

used repeatedly in different locations of the
program.
– Rather than repeat the same instructions several times,
they can be grouped into a subroutine that is called
from the different locations.

• In Assembly language, a subroutine can exist

anywhere in the code.
– However, it is customary to place subroutines
separately from the main program.
 Subroutines

• The 8085 has two instructions for dealing

with subroutines.
– The CALL instruction is used to redirect
program execution to the subroutine.
– The RTE insutruction is used to return the
execution to the calling routine.
 The CALL Instruction

• CALL 4000H
– Push the address of the instruction
immediately following the CALL onto the
2000
s ta c k
C AL L 4000
2 0 0 3wit h the 16-bi t
– Load the program PC
counter
2003

address supplied with the CALL in struction.

FFFB
FFFC

FFFD 03
20 SP
FFFE

FFFF
 The RET Instruction

• RET
– Retrieve the return address from the top of
the stack
– Load the program counter with the return
address. PC 2003
FFFB
4014 ...
4015 RTE FFFC SP
03
FFFD 20

FFFE

FFFF
 Cautions

• The CALL instruction places the return address at

the two memory locations immediately before
where the Stack Pointer is pointing.
– You must set the SP correctly BEFORE using the
CALL instruction.

• The RTE instruction takes the contents of the two

memory locations at the top of the stack and uses
these as the return address.
– Do not modify the stack pointer in a subroutine. You
will loose the return address.
 Passing Data to a Subroutine

• In Assembly Language data is passed to a

subroutine through registers.
– The data is stored in one of the registers by the calling
program and the subroutine uses the value from the
register.

• The other possibility is to use agreed upon

memory locations.
– The calling program stores the data in the memory
location and the subroutine retrieves the data from the
location and uses it.
 Call by Reference and Call
by Value
• If the subroutine performs operations on the
contents of the registers, then these modifications
will be transferred back to the calling program
upon returning from a subroutine.
– Call by reference

• If this is not desired, the subroutine should PUSH

all the registers it needs on the stack on entry
and POP them on return.
– The original values are restored before execution
returns to the calling program.
 Cautions with PUSH and POP

• PUSH and POP should be used in opposite order.

• There has to be as many POP’s as there are

PUSH’s.
– If not, the RET statement will pick up the wrong
information from the top of the stack and the program
will fail.

• It is not advisable to place PUSH or POP inside a

loop.
 Conditional CALL and RTE
Instructions
• The 8085 supports conditional CALL and
conditional RTE instructions.
– The same conditions used with conditional JUMP
instructions can be used.

– CC, call subroutine if Carry flag is set.

– CNC, call subroutine if Carry flag is not set
– RC, return from subroutine if Carry flag is set
– RNC, return from subroutine if Carry flag is not
set
– Etc.
 A Proper Subroutine

• According to Software Engineering practices, a

proper subroutine:
– Is only entered with a CALL and exited with an
RTE
– Has a single entry point
• Do not use a CALL statement to jump into different points of
the same subroutine.
– Has a single exit point
• There should be one return statement from any subroutine.

• Following these rules, there should not be any

confusion with PUSH and POP usage.
 INTERRUPT
 Interrupt is a signal send by an external device to the processor, to the
processor to perform a particular task or work. Mainly in the microprocessor
based system the interrupts are used for data transfer between the peripheral
and the microprocessor.

 Types of Interrupts
 The interrupts are classified into software interrupts and hardware interrupts.

 •The software interrupts are program instructions. These instructions are

inserted at desired locations in a program. While running a program, lf a
software interrupt instruction is encountered, then the processor executes an
interrupt service routine (ISR).

 •The hardware interrupts are initiated by an external device by placing an

appropriate signal at the interrupt pin of the processor. If the interrupt is
accepted, then the processor executes an interrupt service routine (ISR).
 SOFTWARE INTERRUPTS OF 8085
 When the processor encounters the software instruction, it pushes the content of PC(Program
Counter) to stack. Then loads the Vector address in PC and starts executing the Interrupt
Service Routine (ISR) stored in this vector address.

 At the end of ISR, a return instruction – RET will be placed. When the RET instruction is
executed, the processor POP the content of stack to PC. Hence the processor control returns
to the main program after servicing the interrupt.
 .

Interrupt Vector address

RST0 0000H
RST1 0008H
RST2 0010H
RST3 0018H
RST4 0020H
RST5 0028H
RST6 0030H
RST7 0038H
 HARDWARE INTERRUPTS OF 8085

 An external device, initiates the hardware interrupts of 8085 by placing an

appropriate signal at the interrupt pin of the processor.

 The processor keeps on checking the interrupt pins at the second T-state
of last machine cycle of every instruction.
 If the processor finds a valid interrupt signal and if the interrupt is
unmasked and enabled, then the processor accepts the interrupt.
 The acceptance of the interrupt is acknowledged by sending an INTA signal
to the interrupted device.
 The processor saves the content of PC (program Counter) in stack and then
loads the vector address of the interrupt in PC. (If the interrupt is non-
vectored, then the interrupting device has to supply the address of ISR
when it receives INTA signal).
 It starts executing ISR in this address.
 At the end of ISR, a return instruction, RET will be placed.
 When the processor executes the RET instruction, it POP the content of
top of stack to PC. Thus the processor control returns to main program
after servicing interrupt.
 Further the interrupts may be classified into VECTORED and NON-
VECTORED INTERRUPTS. 

 1. VECTORED INTERRUPT- In vectored interrupts, the processor

automatically branches to the specific address in response to an
interrupt. 

 2. NON-VECTORED INTERRUPT- But in non-vectored interrupts the

interrupted device should give the address of the interrupt service
routine (ISR).
  
 8085 VECTOR INTERRUPTS
 In vectored interrupts, the manufacturer fixes the address of the ISR to which the
program control is to be transferred. The vector addresses of hardware interrupts
are given in table as shown below:

 The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts. The INTR is a
non-vectored interrupt. Hence when a device interrupts through INTR, it has to
supply the address of ISR after receiving interrupt acknowledge signal.

 The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the
interrupt signal has to make a low to high transition and then it has to remain
high until the interrupt is recognized.

 The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5,
the interrupt signal has to make a low to high transition an it need not remain
high until it is recognized.

 The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these
interrupts the interrupting signal should remain high, until it is recognized.
Interrupt Vector address

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002CH

TRAP 0024H
 MASKABLE & NON-MASKABLE INETRRUPTS:

 The hardware vectored interrupts are classified into maskable and non-
maskable interrupts.
  
 •TRAP is non-maskable interrupt
  
 •RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt. Masking is preventing
the interrupt from disturbing the main program. When an interrupt is masked
the processor will not accept the interrupt signal. The interrupts can be
masked by moving an appropriate data (or code) to accumulator and then
executing SIM instruction. (SIM - Set InterruptMask). All the hardware
interrupts, except TRAP are disabled, when the processor is resetted. They
can also be disabled by executing Dl instruction. (Dl-Disable Interrupt).
  
 •When an interrupt is disabled, it will not be accepted by the processor.
(i.e., INTR, RST 5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and
upon hardware reset).
  
 •To enable (to allow) the disabled interrupt, the processor has to execute El
instruction (El-Enable Interrupt.
 The 8085 Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
Interrupt Vectors and the
Vector Table
• An interrupt vector is a pointer to where the ISR is
stored in memory.
• All interrupts (vectored or otherwise) are mapped
onto a memory area called the Interrupt Vector
Table (IVT).
– The IVT is usually located in memory page 00
(0000H
- 00FFH).
– The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when an
interrupt arrives.
– The IVT is divided into several blocks. Each block is
used by one of the interrupts to hold its “vector”
The 8085 Non-Vectored Interrupt
Process
1. The interrupt process should be enabled using
the EI instruction.
2. The 8085 checks for an interrupt during
the execution of every instruction.
3. If there is an interrupt, the microprocessor
will complete the executing instruction, and
start a RESTART sequence.
4. The RESTART sequence resets the interrupt flip
flop and activates the interrupt acknowledge
signal (INTA).
5. Upon receiving the INTA signal, the interrupting
device is expected to return the op-code of one
of the 8 RST instructions.
The 8085 Non-Vectored
Interrupt
Processexecutes the RST
6. When the microprocessor
instruction received from the device, it saves
the address of the next instruction on the stack
and jumps to the appropriate entry in the IVT.
7. The IVT entry must redirect the microprocessor to
the actual service routine.
8. The service routine must include the instruction
EI to re-enable the interrupt process.
9. At the end of the service routine, the RET
instruction returns the execution to where
the program was interrupted.
 The 8085 Non-Vectored Interrupt
Process Restart Equivalent
Instruction to
RST0 CALL

0000H
• The 8085 recognizes 8 RESTART RST1 CALL

instructions: RST0 - RST7. 0008H

– each of these would send the RST2 CALL
execution to a predetermined 0010H
hard-wired memory RST3 CALL
location:
0018H
RST4 CALL

0020H
RST5 CALL

0028H
RST6 CALL
 Restart Sequence

• The restart sequence is made up of three machine

cycles
– In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor reads the data lines
expecting to receive, from the interrupting device, the opcode
for the specific RST instruction.
– In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is saved on the
stack.
• Then the microprocessor jumps to the address associated with
the specified RST instruction.
 Restart Sequence

• The location in the IVT associated with the

RST instruction can not hold the complete
service routine.
– The routine is written somewhere else in
memory.
– Only a JUMP instruction to the ISR’s location
is kept in the IVT block.
 Hardware Generation of RST
Opcode
• How does the external device produce the
opcode for the appropriate RST instruction?
– The opcode is simply a collection of bits.
– So, the device needs to set the bits of the data
bus to the appropriate value in response to
an INTA signal.
 Hardware Generation of RST
The following is an
Opcode
example of generating
RST 5:

RST 5’s opcode is EF =

D D
76543210
11101111
 Hardware Generation of RST
Opcode
• During the interrupt acknowledge machine cycle,
(the 1st machine cycle of the RST operation):
– The Microprocessor activates the INTA signal.
– This signal will enable the Tri-state buffers, which will
place the value EFH on the data bus.
– Therefore, sending the Microprocessor the RST 5
instruction.

• The RST 5 instruction is exactly equivalent to

CALL 0028H
 Issues in Implementing INTR
Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock
cycle before the last T-state of each instruction.
– The interrupt process is Asynchronous.
– The INTR must remain active long enough to allow for
the longest instruction.
– The longest instruction for the 8085 is the conditional
CALL instruction which requires 18 T-states.

Therefore, the INTR must remain active for 17.5

T-states.
 Issues in Implementing INTR
Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
– The worst case situation is when EI is the first
instruction in the ISR.
– Once the microprocessor starts to respond to an INTR
interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as the

INTA signal is received.
 Issues in Implementing INTR
Interrupts
• Can the microprocessor be interrupted again
before the completion of the ISR?
– As soon as the 1st interrupt arrives, all maskable
interrupts are disabled.
– They will only be enabled after the execution of the EI
instruction.

Therefore, the answer is: “only if you allow it to”.

If the EI instruction is placed early in the ISR, other
interrupt may occur before the ISR is done.
 Multiple Interrupts & Priorities

• How do we allow multiple devices to

interrupt using the INTR line?
– The microprocessor can only respond to one
signal on INTR at a time.
– Therefore, we must allow the signal from only
one of the devices to reach the microprocessor.
– We must assign some priority to the different
devices and allow their signals to reach the
microprocessor according to the priority.
 The Priority Encoder

• The solution is to use a circuit called the priority

encoder (74366).
– This circuit has 8 inputs and 3 outputs.
– The inputs are assigned increasing priorities according
to the increasing index of the input.
• Input 7 has highest priority and input 0 has the lowest.
– The 3 outputs carry the index of the highest priority
active input.
– Figure 12.4 in the book shoes how this circuit can be
used with a Tri-state buffer to implement an
interrupt priority scheme.
• The figure in the textbook does not show the method for
distributing the INTA signal back to the individual devices.
 Multiple Interrupts & Priorities

• Note that the opcodes for the different RST

instructions follow a set pattern.
• Bit D5, D4 and D3 of the opcodes change in a binary
sequence from RST 7 down to RST 0.
• The other bits are always 1.
• This allows the code generated by the 74366 to be used
directly to choose the appropriate RST instruction.

• The one draw back to this scheme is that the only

way to change the priority of the devices
connected to the 74366 is to reconnect the
hardware.
 Multiple Interrupts and Priority
INTR Circuit
Dev. 7 O7
INTA
7 Circuit
O6 4
Dev. 6 RST Circuit
O5
1
Dev. 5
3 +5 V
O4 8
Dev. 4 O3
INTA
O2 INTR
Dev. 3
I7 AD7
8
O1
Dev. 2
AD6 0
AD5
I6 O0
AD4
Dev. 1 7 8
AD3
I5
Tri – AD2 5
Dev. 0 State AD1
4 Buffer
I4Priority
AD0
IEncoder
3

3
 The 8085
Maskable/Vector
• The 8085 has 4 ed Interruptsinterrupt inputs.
Masked/Vectored
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following
table:
Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the
RST instructions. That’s why they have names like RST 5.5
(RST 5 and a half).
Masking RST 5.5, RST 6.5 and
RST 7.5
• These three interrupts are masked at two
levels:
– Through the Interrupt Enable flip flop and the
EI/DI instructions.
• The Interrupt Enable flip flop controls the whole
maskable interrupt process.
– Through individual mask flip flops that control
the availability of the individual interrupts.
• These flip flops control the interrupts individually.
 Maskable Interrupts
RST7.5 Memory
RST 7.5

M 7.5

RST 6.5

M 6.5

RST 5.5

M 5.5

INTR

Interrupt
Enable
Flip Flop
 The 8085
Maskable/Vectore
1. d process
The interrupt Interruptshould be enabled using
the EI instruction.
2. Process
The 8085 checks for an interrupt during
the execution of every instruction.
3. If there is an interrupt, and if the interrupt
is enabled using the interrupt mask, the
microprocessor will complete the executing
instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call
instruction that sends the execution to the
appropriate location in the interrupt vector table.
 The 8085
Maskable/Vectore
5. When thed microprocessor
Interruptexecutes the
call instruction, it saves the address of the
Process
next instruction on the stack.
6. The microprocessor jumps to the specific
service routine.
7. The service routine must include the instruction
EI to re-enable the interrupt process.
8. At the end of the service routine, the RET
instruction returns the execution to where
the program was interrupted.
 Manipulating the Masks

• The Interrupt Enable flip flop is manipulated using

the EI/DI instructions.

• The individual masks for RST 5.5, RST 6.5 and

RST 7.5 are manipulated using the SIM
instruction.
– This instruction takes the bit pattern in the Accumulator
and applies it to the interrupt mask enabling and
disabling the specific interrupts.
 How SIM Interprets the
Accumulator
7 6 5 4 3 2 1 0

M5.5
M7.5

M6.5
MSE
SDO

R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 1 - Available
RST6.5 Mask
2 - Masked
RST7.5
Mask

Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to 1 - Set the masks according
SOD pin to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

 SIM and the Interrupt Mask

• Bit 0 is the mask for RST 5.5, bit 1 is the mask for
RST 6.5 and bit 2 is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

• Bit 3 (Mask Set Enable - MSE) is an enable for

setting the mask.
• If it is set to 0 the mask is ignored and the old settings
remain.
• If it is set to 1, the new setting are applied.
• The SIM instruction is used for multiple purposes and not only
for setting interrupt masks.
– It is also used to control functionality such as Serial Data
Transmission.
– Therefore, bit 3 is necessary to tell the microprocessor
whether or not the interrupt masks should be modified
 SIM and the Interrupt Mask

• The RST 7.5 interrupt is the only 8085 interrupt that has
memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will
remember the signal.
– When RST7.5 is unmasked, the microprocessor will be interrupted
even if the device has removed the interrupt signal.
– This flip flop will be automatically reset when the microprocessor
responds to an RST 7.5 interrupt.

• Bit 4 of the accumulator in the SIM instruction allows

explicitly resetting the RST 7.5 memory even if the
microprocessor did not respond to it.
 SIM and the Interrupt Mask
• The SIM instruction can also be used to perform
serial data transmission out of the 8085’s SOD
pin.
– One bit at a time can be sent out serially over the SOD
pin.

• Bit 6 is used to tell the microprocessor whether or

not to perform serial data transmission
• If 0, then do not perform serial data transmission
• If 1, then do.
• The value to be sent out on SOD has to be placed
in bit 7 of the accumulator.

• Bit 5 is not used by the SIM instruction

 Using the SIM Instruction to Modify
the Interrupt Masks
• Example: Set the interrupt masks so that
RST5.5 is enabled, RST6.5 is masked, and
RST7.5 is enabled.
– First, determine the contents of the
accumulator

M7.5

M6.5

M5.5
SDO

MSE
R7.5
SDE

XXX
- Enable 5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0 0 0 0 0 1 0 1 0
- Allow setting the masks bit 3 = 1
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0 Contents of accumulator are: 0AH
- Don’t use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0

EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
 Triggering
Levels
• RST 7.5 is positive edge sensitive.
• When a positive edge appears on the RST7.5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt.
• Since the value has been stored in the flip flop, the line does
not have to be high when the microprocessor checks for the
interrupt to be recognized.
• The line must go to zero and back to one before a new interrupt
is recognized.

• RST 6.5 and RST 5.5 are level sensitive.

• The interrupting signal must remain present until the
microprocessor checks for interrupts.
 Determining the Current Mask
Settings
• RIM instruction: Read Interrupt Mask
– Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin and
mask.
RST7.5 Memory
RST 7.5
M 7.5
7 6 5 4 3 2 1 0
M7.5

M6.5

M5.5
P5.5
P7.5
P6.5
SDI

IE

RST 6.5

M 6.5

RST 5.5
M 5.5

Interrupt Enable
Flip Flop
How RIM sets the
Accumulator’s
different bits 7 6 5 4 3 2 1 0

M5.5
M6.5
M7.5
P6.5
P7.5

P5.5
SDI

IE
}
RST5.5 Mask
Serial Data In 1 - Available
RST6.5 Mask
2 - Masked
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt
Pending RST7.5 Interrupt Enable
Value of the Interrupt Enable
Interrupt Pending
Flip Flop
 The RIM Instruction and the
Masks
• Bits 0-2 show the current setting of the mask for
each of RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip flops.
• They can be used by a program to read the mask settings in
order to modify only the right mask.

• Bit 3 shows whether the maskable interrupt

process is enabled or not.
• It returns the contents of the Interrupt Enable Flip
Flop.
• It can be used by a program to determine whether or not
interrupts are enabled.
 The RIM Instruction and the
Masks
• Bits 4-6 show whether or not there are pending
interrupts on RST 7.5, RST 6.5, and RST 5.5
• Bits 4 and 5 return the current value of the RST5.5 and RST6.5
pins.
• Bit 6 returns the current value of the RST7.5 memory flip flop.

• Bit 7 is used for Serial Data Input.

• The RIM instruction reads the value of the SID pin on the
microprocessor and returns it in this bit.
 Pending Interrupts

• Since the 8085 has five interrupt lines, interrupts

may occur during an ISR and remain pending.
– Using the RIM instruction, the programmer can read
the status of the interrupt lines and find if there are any
pending interrupts.

– The advantage is being able to find about interrupts on

RST 7.5, RST 6.5, and RST 5.5 without having to
enable low level interrupts like INTR.
 Using RIM and SIM to set
Individual Masks
• Example: Set the mask to enable RST6.5 without
modifying the masks for RST5.5 and RST7.5.
– In order to do this correctly, we need to use the RIM
instruction to find the current settings of the
RST5.5 and RST7.5 masks.
– Then we can use the SIM instruction to set the masks
using this information.
– Given that both RIM and SIM use the Accumulator, we
can use some logical operations to masks the un-
needed values returned by RIM and turn them into the
values needed by SIM.
 Using RIM and SIM to set
Individual Masks
– Assume the RST5.5 and RST7.5 are enabled and the interrupt process
is disabled. Accumulator

M7.5

M6.5

M5.5
P6.5
P7.5

P5.5
SDI

IE
RIM ; Read the current settings.
0 0 0 0 0 0 1 0

ORI 08H ;00001000 0 0 0 0 1 0 1 0

; Set bit 4 for MSE.

ANI 0DH ;00001101 0 0 0 0 1 0 0 0

; Turn off Serial Data, Don’t reset
; RST7.5 flip flop, and set the mask
; for RST6.5 off. Don’t cares are
; assumed to be 0.
0 0 0 0 1 0 0 0
SIM ; Apply the settings.

M6.5
M7.5
R7.5
SDO
SDE

XXX

MSE
 TRAP

• TRAP is the only non-maskable interrupt.

– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until
it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
 Internal Interrupt Priority

• Internally, the 8085 implements an interrupt

priority scheme.
– The interrupts are ordered as follows:
• TRAP
• RST 7.5
• RST 6.5
• RST 5.5
• INTR

– However, TRAP has lower priority than the HLD signal

used for DMA.
 The 8085 Interrupts
Interrupt Masking Triggerin
Maskable Vectored Memory
Name g
Method Method
Level
INTR Yes DI / EI No No
Sensitive
RST 5.5 / DI / EI Level
Yes Yes No
RST 6.5 SIM Sensitive
DI / EI Edge
RST 7.5 Yes Yes Yes
SIM Sensitive
Level &
TRAP No None Yes No Edge
Sensitive