Process Synchn-2
Process Synchn-2
Synchronization Hardware
• Many systems provide hardware support for critical section
code
• Uniprocessors – could disable interrupts
– Currently running code would execute without
preemption
– Generally too inefficient on multiprocessor systems
• Operating systems using this not broadly scalable
• Modern machines provide special atomic hardware
instructions
• Atomic = non-interruptable
– Either test memory word and set value
– Or swap contents of two memory words
Test-and-Set Instruction
• Definition:
• Definition:
Remainder Section
until false
Proof
• How ME Reqmt met
Process Pi can enter its CS only if either waiting[i] =
false or key = false.
key can become false only if Test-and-Set is executed.
First process to execute Test-and-Set will find key=false;
all others must wait
waiting[i] can become false only if another process leaves
CS.
Only one waiting[i] is set to false
Proof…
• How Progress Reqmt is met?
A process exiting the CS either sets lock to false
or sets waiting[j] to false
Both allow a process to enter its CS
• How Bounded waiting is met?
A process leaving CS scans the array waiting in
the cyclic ordering (i+1, i+2, …n-1,0,1,2..,i-1)
The first process in this ordering with
waiting[j]=true is designated to enter CS. Any
process waiting to enter CS will do so within n-1
turns.
Semaphores
Fundamental Principle
• Two or more processes can cooperate by means of
simple signals, such that a process can be forced to stop
at a specified place until it has received a specific signal.
s=1 C D B
Suspended List Semaphore Ready List
Processor
2
B
s=0 A C D
Suspended List Semaphore Ready List
Processor
3
D
B s=-1 A C
Suspended List Semaphore Ready List
4 Processor
D
s=0 B A C
Suspended List Semaphore Ready List
Processor
5
C
s=0 D B A
Suspended List Semaphore Ready List
Processor
6
D
B A C s= -3
Suspended List Semaphore Ready List
7 Processor
D
B A s=-2 C
Suspended List Semaphore Ready List
Example of Semaphore Mechanism
1. A is running; B, C and D are ready; semaphore count is 1, indicating that one of
D’s result is available. When A executes a wait instruction, it immediately passes
the semaphore and continue to execute; subsequently it rejoins the ready queue.
6. C is suspended when it issues a wait instruction. Similarly A and B are run and
are suspended on the semaphore allowing D to resume execution.
7. When D has a result, it issues a signal, which transfers C to the ready list.
pi pi
1 0
pj pj
signal
(a) (b)
mutex mutex
pi
pi
1
0
pj
pj
Perform action ak
Signalling using Semaphores
…….. …….
Perform action ai Perform action aj
Wait(sync) Signal(sync)
Perform action ak …………..
………..
Process Pi Process Pj
Signalling using Semaphores
• Before performing action ak, process Pi
should be made to wait till it receives a
signal from Pj, indicating that it has
performed action aj.